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1. 发明专利

JP2014045183A Semiconductor structure, semiconductor device, and method for producing semiconductor structure 有权
标题翻译：半导体结构，半导体器件及其半导体结构的制造方法
公开(公告)号：JP2014045183A
公开(公告)日：2014-03-13
申请号：JP2013158582
申请日：2013-07-31
申请人： National Institute Of Advanced Industrial & Technology , 独立行政法人産業技術総合研究所 , Central Research Institute Of Electric Power Industry , 一般財団法人電力中央研究所 , Kansai Electric Power Co Inc:The , 関西電力株式会社
发明人： KOJIMA KAZUSATO , JI SHI-YANG , MIYAZAWA TETSUYA , TSUCHIDA SHUICHI , NAKAYAMA KOJI , ITSUMI TETSURO , ASANO KATSUNORI
IPC分类号： H01L21/205 , H01L21/336 , H01L29/12 , H01L29/739 , H01L29/78
CPC分类号： H01L29/1608 , C30B25/20 , C30B29/36 , H01L21/02378 , H01L21/02433 , H01L21/02529 , H01L21/02576 , H01L21/02579 , H01L21/0259 , H01L21/02609 , H01L21/0262 , H01L21/046 , H01L29/04 , H01L29/045 , H01L29/167 , H01L29/66068 , H01L29/7393 , H01L29/7395
摘要： PROBLEM TO BE SOLVED: To provide: a semiconductor structure excellent in mechanical strength and capable of being reduced in resistance during conduction of electricity; a semiconductor device; and a method for producing the semiconductor structure.SOLUTION: A semiconductor structure of the present invention has at least an α-type crystal structure, contains aluminum at an impurity concentration of 1×10cmor higher, and has a p-type silicon carbide single crystal layer having a thickness of 50 μm or higher. Moreover, a method for producing the semiconductor structure of the present invention includes at least an epitaxial growth step where silicon carbide source and an aluminum source are introduced, and a p-type silicon carbide single crystal layer is epitaxially grown on a substrate layer of silicon carbide single crystals having an α-type crystal structure. The epitaxial growth step is performed under temperature conditions of 1,500°C or above and 1,700°C or below and under pressure conditions of 5×10Pa or more and 25×10Pa or less.
摘要翻译：要解决的问题：提供：机械强度优异并且能够在电传导期间电阻降低的半导体结构; 半导体器件; 以及制造半导体结构的方法。本发明的半导体结构至少具有α型晶体结构，其含有杂质浓度为1×10cm以上的铝，并具有p型碳化硅单晶层的厚度为50μm以上。此外，本发明的半导体结构体的制造方法至少包括引入碳化硅源和铝源的外延生长工序，在硅衬底层上外延生长p型碳化硅单晶层具有α型晶体结构的碳化物单晶。外延生长步骤在1500℃以上且1700℃以下的温度条件下，在5×10Pa以上且25×10Pa以下的压力条件下进行。

2. 发明专利

JP2013107788A Method for manufacturing silicon carbide wafer, silicon carbide wafer, silicon carbide semiconductor element, and power converting device 有权
标题翻译：制造硅碳化硅，碳化硅陶瓷，碳化硅半导体元件和功率转换器件的方法
公开(公告)号：JP2013107788A
公开(公告)日：2013-06-06
申请号：JP2011253283
申请日：2011-11-18
申请人： Central Research Institute Of Electric Power Industry , 一般財団法人電力中央研究所 , Kansai Electric Power Co Inc:The , 関西電力株式会社
发明人： NAGANO MASAHIRO , TSUCHIDA SHUICHI , NAKAYAMA KOJI , ASANO KATSUNORI
IPC分类号： C30B29/36 , C30B25/20
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a silicon carbide wafer which prevents complication of a manufacture process, does not restrict a silicon carbide substrate, and is capable of more surely converting a basal plane dislocation (BPD) to a threading edge dislocation (TED).SOLUTION: This method includes the first step in which Si ion is injected into one direction of a silicon carbide substrate 1 or the substrate 1 is irradiated with an electron beam, the second step in which the silicon carbide substrate 1 is subjected to annealing, and the third step in which one direction side of the silicon carbide substrate 1 is epitaxially grown to form an epitaxial film 3. The ion to be injected into the silicon carbide substrate is at least one kind selected from a group comprising Si ion, C ion, H ion, He ion, P ion, Al ion B ion and N ion.
摘要翻译：要解决的问题：为了提供一种防止制造工艺的复杂化的碳化硅晶片的制造方法，不限制碳化硅衬底，并且能够更可靠地将基面位错（BPD）转换为穿线边缘错位（TED）。解决方案：该方法包括将Si离子注入到碳化硅衬底1的一个方向或者将衬底1照射电子束的第一步骤，其中碳化硅衬底1经受第二步骤退火，以及第三步骤，其中外延生长碳化硅衬底1的一个方向侧以形成外延膜3.要注入到碳化硅衬底中的离子是选自由以下组成的组中的至少一种：Si离子， C离子，H离子，He离子，P离子，Al离子B离子和N离子。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2012246168A Silicon carbide substrate, silicon carbide wafer, method for manufacturing silicon carbide wafer, and silicon carbide semiconductor device 有权
标题翻译：硅碳化硅基体，碳化硅陶瓷，制造碳化硅陶瓷的方法和碳化硅半导体器件
公开(公告)号：JP2012246168A
公开(公告)日：2012-12-13
申请号：JP2011118419
申请日：2011-05-26
申请人： Central Research Institute Of Electric Power Industry , 一般財団法人電力中央研究所 , Kansai Electric Power Co Inc:The , 関西電力株式会社
发明人： TSUCHIDA SHUICHI , CHO MEGURU , NAKAYAMA KOJI , ASANO KATSUNORI
IPC分类号： C30B29/36 , C23C16/02 , C23C16/42 , C30B25/20 , C30B33/02
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a silicon carbide wafer which prevents complication of a manufacture process, does not restrict a silicon carbide substrate, and is capable of more surely converting a basal plane dislocation to a threading edge dislocation, and also to provide a silicon carbide semiconductor device using the silicon carbide wafer.SOLUTION: The tip part of the basal plane dislocation 20 of the silicon carbide substrate 1 is converted to the threading edge dislocation 30 by heat-treating the silicon carbide substrate 1 at 1,700-2,200°C in an inert gas atmosphere or in a vacuum, and an epitaxial film 2 where the basal plane dislocation 20 is reduced is crystal-grown by carrying out epitaxial growth of silicon carbide on the silicon carbide substrate 1.
摘要翻译：要解决的问题：为了提供一种制造碳化硅晶片的方法，其防止制造工艺的复杂化，不限制碳化硅衬底，并且能够更可靠地将基面位错转换为螺纹刃错位并且还提供使用碳化硅晶片的碳化硅半导体器件。解决方案：通过在惰性气体气氛中在1700-2200℃下热处理碳化硅衬底1将碳化硅衬底1的基面位错20的尖端部分转换成穿线边缘位错30 真空和通过在碳化硅衬底1上进行碳化硅的外延生长而使基面位错20被还原的外延膜2被晶体生长。（C）2013，JPO＆INPIT

4. 发明专利

JP2012028565A Bipolar semiconductor device manufacturing method and bipolar semiconductor device 审中-公开
标题翻译：双极半导体器件制造方法和双极半导体器件
公开(公告)号：JP2012028565A
公开(公告)日：2012-02-09
申请号：JP2010165938
申请日：2010-07-23
申请人： Kansai Electric Power Co Inc:The , 関西電力株式会社
发明人： NAKAYAMA KOJI
IPC分类号： H01L29/861 , H01L21/205 , H01L21/329 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/12 , H01L29/161 , H01L29/732 , H01L29/739 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a bipolar semiconductor device manufacturing method, which allows the prevention of increase in forward voltage even under conditions including a high temperature and a high current density, and to provide a bipolar semiconductor device.SOLUTION: The bipolar semiconductor device manufacturing method includes a manufacturing process of a SiC pin diode 20. The manufacturing process includes forming, on C plane of an n type 4HSiC substrate 21, a buffer layer 22, which is an n type SiC growth layer, a drift layer 23, a p type junction layer 24 and a p+ type contact layer 25, and thereafter removing the whole n type 4HSiC substrate 21 by chemical mechanical polishing (CMP). Thus, it becomes possible to avoid the phenomenon that minority carriers having reached the substrate escalate a basal plane dislocation included in the substrate into a stacking fault when passing a forward current through the device.
摘要翻译：解决的问题：提供即使在包括高温和高电流密度的条件下也能够防止正向电压增加的双极半导体器件制造方法，并且提供双极型半导体器件。解决方案：双极半导体器件制造方法包括SiC pin二极管20的制造工艺。制造工艺包括在n型4HSiC衬底21的C平面上形成作为n型SiC的缓冲层22 生长层，漂移层23，p型接合层24和p +型接触层25，然后通过化学机械抛光（CMP）除去整个n型4HSiC基板21。因此，可以避免当使正向电流通过器件时，到达衬底的少数载流子使包括在衬底中的基底面错位升高成堆垛层错。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2011151136A Bipolar semiconductor device 审中-公开
标题翻译：双极半导体器件
公开(公告)号：JP2011151136A
公开(公告)日：2011-08-04
申请号：JP2010010231
申请日：2010-01-20
申请人： Kansai Electric Power Co Inc:The , 関西電力株式会社
发明人： NAKAYAMA KOJI , SUGAWARA YOSHITAKA
IPC分类号： H01L21/60
CPC分类号： H01L24/05 , H01L24/06 , H01L2224/04042 , H01L2224/05553 , H01L2224/48 , H01L2224/4845 , H01L2224/4847 , H01L2224/85 , H01L2224/85205 , H01L2224/85206 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01014 , H01L2924/01031 , H01L2924/01033 , H01L2924/1301 , H01L2924/1305 , H01L2224/05556 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a bipolar semiconductor device that suppresses generation of a surface defect, and prevents a forward voltage from rising. SOLUTION: A gate turn-off thyristor has bonding wires 23 extended in a first direction (length direction) P of mesa type p-type anode emitter layers 4. An ultrasonic wave and force of weighting in wiring bonding are applied, therefore, from the bonding wire 23 to ends 4C and 4D which are ends of the respective mesa type p-type anode emitter layers 4 in the first direction (length direction) P, and extend in the second direction (width direction) S through anode electrodes 12. Then surface defects 25 generated in the respective mesa type p-type anode emitter layers 4 by the ultrasonic wave and force of weighting in the wire bonding, are generated at the ends 4C and 4D which are shorter in dimension than ends 4A and 4B of the mesa type p-type anode emitter layers 4 which extend in the first direction. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供抑制表面缺陷的产生并防止正向电压上升的双极半导体器件。栅极截止晶闸管具有沿台阶型p型阳极发射极层4的第一方向（长度方向）P延伸的接合线23.应用超声波和布线接合中的加权力，因此从第一方向（长度方向）P的各台阶型p型阳极发射极层4的端部的接合线23到端部4C，4D，在第二方向（宽度方向）S上通过阳极电极然后在端部4C和4D处产生在相应的台面型p型阳极发射极层4中通过超声波和引线接合中的加权力产生的表面缺陷25，其尺寸比端部4A和4B短的沿着第一方向延伸的台面型p型阳极发射极层4。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2010147083A Gate turnoff thyristor device and bipolar transistor apparatus 审中-公开
标题翻译：门式开关装置和双极晶体管装置
公开(公告)号：JP2010147083A
公开(公告)日：2010-07-01
申请号：JP2008319835
申请日：2008-12-16
申请人： Kansai Electric Power Co Inc:The , 関西電力株式会社
发明人： ISHII RYUSUKE , NAKAYAMA KOJI , SUGAWARA YOSHITAKA
IPC分类号： H01L29/744 , H01L29/74 , H01L29/861 , H01L29/866
摘要： PROBLEM TO BE SOLVED: To provide a gate turnoff thyristor device that prevents failure, from being caused between anode and a gate by a surge voltage due to an off-gate current, and achieves miniaturization.
SOLUTION: The SiC GTO device can control a surge voltage, generated between an anode electrode 12 and a gate electrode 13 by an off-gate current, by using a zener diode structural part 6. Further, the zener diode structural part 6 is incorporated in the GTO element that is made up by an n-type SiC substrate 1, an n-type SiC buffer layer 2, a p-type SiC buffer layer 3, a p-type SiC drift layer 4, an n-type SiC base layer 5, a p-type SiC anode layer 7, and a p-type SiC contact layer 8, thereby the device can be miniaturized compared to the case where the zener diode is arranged separately from the GTO device.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供防止由于栅极电流引起的浪涌电压在阳极和栅极之间的故障的栅极截止晶闸管器件，并且实现小型化。解决方案：通过使用齐纳二极管结构部分6，SiC GTO器件可以通过栅极电流来控制在阳极电极12和栅电极13之间产生的浪涌电压。此外，齐纳二极管结构部分6 被结合在由n型SiC衬底1，n型SiC缓冲层2，p型SiC缓冲层3，p型SiC漂移层4，n型 SiC基底层5，p型SiC阳极层7和p型SiC接触层8，因此与齐纳二极管与GTO器件分开布置的情况相比，可以使器件小型化。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2005167035A Silicon carbide semiconductor device and manufacturing method thereof 审中-公开
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2005167035A
公开(公告)日：2005-06-23
申请号：JP2003405259
申请日：2003-12-03
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： NAKAYAMA KOJI , SUGAWARA YOSHITAKA , ASANO KATSUNORI , TSUCHIDA SHUICHI , KAMATA ISAO , MITSUYANAGI TOSHIYUKI , NAKAMURA TOMONOBU
IPC分类号： H01L21/331 , H01L21/04 , H01L21/329 , H01L21/336 , H01L29/04 , H01L29/12 , H01L29/24 , H01L29/73 , H01L29/739 , H01L29/78 , H01L29/861
CPC分类号： H01L29/868 , H01L29/045 , H01L29/0619 , H01L29/1608 , H01L29/66068 , H01L29/73 , H01L29/7397
摘要： PROBLEM TO BE SOLVED: To prevent the increase of a forward voltage due to aging of a bipolar semiconductor device using a silicon carbide semiconductor.
SOLUTION: The plane having an off-angle θ as 8° with respect to the (000-1) carbon plane of a silicon carbide semiconductor crystal is made to be a growth plane of crystal. A buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on this growth plane with an increase speed of the film thickness per hour (h) which is not less than 3 times larger than that in the prior art, i.e. with film formation speed of 10 μm/h. The flow rate of the raw material gases, which are silane, propane, and a dopant gas are greatly increased to increase the film formation speed.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了防止由于使用碳化硅半导体的双极性半导体器件的老化引起的正向电压的增加。解决方案：将具有相对于碳化硅半导体晶体的（000-1）碳平面的偏角θ为8°的平面制成晶体的生长平面。在该生长平面上形成缓冲层，漂移层和其他p型和n型半导体层，每小时（h）的膜厚度的增加速度不小于先前的3倍即成膜速度为10μm/ h。作为硅烷，丙烷和掺杂剂气体的原料气体的流量大大增加以提高成膜速度。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2012230964A Bipolar semiconductor element and manufacturing method thereof 审中-公开
标题翻译：双极半导体元件及其制造方法
公开(公告)号：JP2012230964A
公开(公告)日：2012-11-22
申请号：JP2011097111
申请日：2011-04-25
申请人： Kansai Electric Power Co Inc:The , 関西電力株式会社
发明人： NISHIMURA MASAHIKO , NAKAYAMA KOJI , MITSUYANAGI YOICHI , ASANO KATSUNORI
IPC分类号： H01L29/868 , H01L21/331 , H01L21/332 , H01L21/336 , H01L29/12 , H01L29/732 , H01L29/739 , H01L29/744 , H01L29/78 , H01L29/861
摘要： PROBLEM TO BE SOLVED: To provide an SiC bipolar semiconductor element which has excellent crystal quality consisting of a p-type SiC substrate.SOLUTION: According to a diode element 1 presented here, a p-type SiC anode layer 12, a p-type SiC drift layer 13 and an n+ type SiC cathode layer 14 are formed on an n-type SiC substrate 21 by epitaxial growth and then the n-type SiC substrate 21 is removed. This means that, since a p+ type 4H-SiC anode layer 12 likened to a p-type substrate is fabricated by epitaxial growth, its crystal growth speed is slower than for a p-type substrate fabricated by bulk growth, so that excellent crystal quality is obtained even when the concentration of aluminum which is a p-type dopant is increased. Therefore, this p+ type 4H-SiC anode layer 12 with excellent crystal quality can be likened to a substrate, making it possible to realize an SiC diode element with excellent crystal quality consisting of a p-type SiC substrate.
摘要翻译：要解决的问题：提供一种具有由p型SiC衬底组成的优异晶体质量的SiC双极半导体元件。解决方案：根据这里所示的二极管元件1，通过在n型SiC衬底21上形成p型SiC阳极层12，p型SiC漂移层13和n +型SiC阴极层14 外延生长，然后去除n型SiC衬底21。这意味着由于通过外延生长制造与p型衬底相似的p +型4H-SiC阳极层12，其晶体生长速度比通过本体生长制造的p型衬底慢，因此优异的晶体质量即使当p型掺杂剂的铝的浓度增加时也是这样。因此，具有优异的晶体质量的p +型4H-SiC阳极层12可以与基板相同，可以实现由p型SiC基板构成的具有优异的晶体质量的SiC二极管元件。版权所有（C）2013，JPO＆INPIT

9. 发明专利

JP2012178412A Bipolar semiconductor element 审中-公开
标题翻译：双极半导体元件
公开(公告)号：JP2012178412A
公开(公告)日：2012-09-13
申请号：JP2011039845
申请日：2011-02-25
申请人： Kansai Electric Power Co Inc:The , 関西電力株式会社
发明人： MITSUYANAGI YOICHI , NAKAYAMA KOJI , ASANO KATSUNORI
IPC分类号： H01L29/868 , H01L21/205 , H01L21/3065 , H01L21/329 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/12 , H01L29/732 , H01L29/739 , H01L29/78 , H01L29/861
摘要： PROBLEM TO BE SOLVED: To provide a SiC bipolar semiconductor element capable of reducing a generation of a surface defect, suppressing a generation of a stacking fault, and an ON-state voltage drift.SOLUTION: A SiC pin diode 20 is made of a silicon carbide semiconductor having a hexagonal crystal structure, of which mesa-shaped semiconductor layer 31 has a hexagonal prism shape. Six side surfaces (mesa surfaces) 31A of the semiconductor layer 31 are all {0m-mn} surfaces (where m and n are integers). Therefore, the angles θ1, θ2 (Fig.4) of Burgers vector BV1, BV2 in direction with respect to the mesa surfaces 31A become smaller than the angles θ101, θ102 (Fig.12) of Burgers vector BV101, BV102 with respect to the element surface (mesa surface) of {11-20} surface, and the length of the Burgers vector BV1, BV2, which is necessary for an occurrence of a surface defect, becomes longer. Thus a surface defect SD on the mesa surfaces 31A becomes less likely to occur, thus reducing a surface defect on each mesa surface 31A of the mesa-shaped semiconductor layer 31 to suppress a generation of a stacking fault.
摘要翻译：要解决的问题：提供能够减少表面缺陷的产生，抑制堆垛层错的产生和导通状态的电压漂移的SiC双极半导体元件。解决方案：SiC pin二极管20由具有六方晶系结构的碳化硅半导体制成，其中台面状半导体层31具有六棱柱形状。半导体层31的六个侧表面（台面）31A都是Θ0m-mn}表面（其中m和n是整数）。因此，汉堡向量BV1，BV2相对于台面31A的<11-20>方向的角度θ1，θ2（图4）变得小于汉堡矢量BV101的角度θ101，θ102（图12） BV102相对于ä11-20}表面的元件表面（台面），并且出现表面缺陷所需的汉堡矢量BV1，BV2的长度变长。因此，不太可能发生台面31A上的表面缺陷SD，从而减小台面状半导体层31的每个台面31A上的表面缺陷，以抑制堆垛层错的产生。版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP2012146932A Bipolar semiconductor element 审中-公开
标题翻译：双极半导体元件
公开(公告)号：JP2012146932A
公开(公告)日：2012-08-02
申请号：JP2011006193
申请日：2011-01-14
申请人： Kansai Electric Power Co Inc:The , 関西電力株式会社
发明人： NAKAYAMA KOJI , ASANO KATSUNORI , MITSUYANAGI YOICHI
IPC分类号： H01L29/744 , H01L21/331 , H01L29/12 , H01L29/732 , H01L29/739 , H01L29/74 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a bipolar semiconductor element which can reduce surface defect and can suppress on voltage drift.SOLUTION: According to this SiC GTO, the extending direction of a long side face 5B of a mesa shape p-type anode emitter layer 5 is inclined by an angle φ=60° from the off direction of direction. The long side face 5B becomes the {01-10} face which is less susceptible to surface defect when compared with a short side face 5C of {11-20} face. Since the extending direction of the long side face 5B is inclined by an angle φ=60° from the off direction, the number of the {0001} face appearing in the long side face 5B of a mesa shape p-type anode emitter layer 5 can be decreased when compared with a case (φ=0°) where the extension direction of the long side face 5B matches the off direction, and thereby the surface defects entering the layer of the {0001} face can be reduced.
摘要翻译：要解决的问题：提供可以减少表面缺陷并且可以抑制电压漂移的双极半导体元件。解决方案：根据该SiC GTO，台面状p型阳极发射极层5的长侧面5B的延伸方向从<11-20>的偏离方向倾斜角度= 60°，方向。与ä11-20}面的短侧面5C相比，长侧面5B成为不易受表面缺陷的面。由于长侧面5B的延伸方向与偏离方向倾斜角度φ= 60°，所以在台面状p型阳极发射极层5的长边面5B出现的ä0001}面的数量可以与长侧面5B的延伸方向与偏离方向一致的情况（φ= 0°）相比，可以减小，从而可以减少进入ä0001}面的层的表面缺陷。版权所有（C）2012，JPO＆INPIT

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