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1. 发明专利

JP2005167035A Silicon carbide semiconductor device and manufacturing method thereof 审中-公开
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2005167035A
公开(公告)日：2005-06-23
申请号：JP2003405259
申请日：2003-12-03
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： NAKAYAMA KOJI , SUGAWARA YOSHITAKA , ASANO KATSUNORI , TSUCHIDA SHUICHI , KAMATA ISAO , MITSUYANAGI TOSHIYUKI , NAKAMURA TOMONOBU
IPC分类号： H01L21/331 , H01L21/04 , H01L21/329 , H01L21/336 , H01L29/04 , H01L29/12 , H01L29/24 , H01L29/73 , H01L29/739 , H01L29/78 , H01L29/861
CPC分类号： H01L29/868 , H01L29/045 , H01L29/0619 , H01L29/1608 , H01L29/66068 , H01L29/73 , H01L29/7397
摘要： PROBLEM TO BE SOLVED: To prevent the increase of a forward voltage due to aging of a bipolar semiconductor device using a silicon carbide semiconductor.
SOLUTION: The plane having an off-angle θ as 8° with respect to the (000-1) carbon plane of a silicon carbide semiconductor crystal is made to be a growth plane of crystal. A buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on this growth plane with an increase speed of the film thickness per hour (h) which is not less than 3 times larger than that in the prior art, i.e. with film formation speed of 10 μm/h. The flow rate of the raw material gases, which are silane, propane, and a dopant gas are greatly increased to increase the film formation speed.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了防止由于使用碳化硅半导体的双极性半导体器件的老化引起的正向电压的增加。解决方案：将具有相对于碳化硅半导体晶体的（000-1）碳平面的偏角θ为8°的平面制成晶体的生长平面。在该生长平面上形成缓冲层，漂移层和其他p型和n型半导体层，每小时（h）的膜厚度的增加速度不小于先前的3倍即成膜速度为10μm/ h。作为硅烷，丙烷和掺杂剂气体的原料气体的流量大大增加以提高成膜速度。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2012004318A Bipolar semiconductor device 审中-公开
标题翻译：双极半导体器件
公开(公告)号：JP2012004318A
公开(公告)日：2012-01-05
申请号：JP2010137578
申请日：2010-06-16
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： NAKAYAMA KOJI , TSUCHIDA SHUICHI , MIYAZAWA TETSUYA
IPC分类号： H01L29/861 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/12 , H01L29/732 , H01L29/739 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a bipolar semiconductor device arranged to prevent minority carriers from reaching a substrate and the forward voltage from increasing even under conditions such as a high temperature and a high current density.SOLUTION: A SiC pin diode 20 has: an n-type SiC substrate 21; an n-type drift layer 23; and an n-type buffer layer 22 formed between the n-type SiC substrate 21 and n-type drift layer 23 and having a thickness of 20 μm. The n-type buffer layer 22 serves as a trap of holes from p-type anode layers 24 and 25, and prevents the holes (minority carriers) from reaching the n-type SiC substrate 21. Since the holes (minority carriers) are prevented from reaching the n-type SiC substrate 21 in this way, a stacking fault can be prevented from spreading from the n-type SiC substrate 21 and therefore the forward voltage can be prevented from increasing.
摘要翻译：要解决的问题：提供一种布置成防止少数载流子到达基板并且正向电压甚至在诸如高温和高电流密度的条件下也增加的双极半导体器件。解决方案：SiC pin二极管20具有：n型SiC衬底21; n型漂移层23; 以及形成在n型SiC衬底21和n型漂移层23之间并具有20μm的厚度的n型缓冲层22。 n型缓冲层22用作p型阳极层24和25的空穴陷阱，并且防止空穴（少数载流子）到达n型SiC衬底21.由于防止了空穴（少数载流子）以这种方式到达n型SiC衬底21时，可以防止堆垛层错从n型SiC衬底21扩散，因此可以防止正向电压增加。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2009010120A Silicon carbide bipolar semiconductor device 有权
标题翻译：碳化硅双极半导体器件
公开(公告)号：JP2009010120A
公开(公告)日：2009-01-15
申请号：JP2007169263
申请日：2007-06-27
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： MITSUYANAGI TOSHIYUKI , TSUCHIDA SHUICHI , KAMATA ISAO , ISHII RYUSUKE , NAKAYAMA KOJI , SUGAWARA YOSHITAKA
IPC分类号： H01L29/861 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/12 , H01L29/732 , H01L29/739 , H01L29/744 , H01L29/78
CPC分类号： H01L2224/32245 , H01L2224/45124 , H01L2224/48247 , H01L2924/12032 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To suppress a stacking fault and an area magnification thereof which make a defective nucleus existing near a front surface of an element as a starting point, and thereby to suppress an increase in forward voltage, in a silicon carbide bipolar semiconductor device with a mesa structure. SOLUTION: The silicon carbide bipolar semiconductor device is constituted by laminating the following in order: a first conductivity-type silicon carbide single crystal substrate; a first conductivity-type silicon carbide drift layer; a second conductivity-type silicon carbide charge injection layer; and a second conductivity-type high doping layer with a doping density higher than that of the silicon carbide charge injection layer. This device is also characterized in that there is provided the mesa structure from the silicon carbide drift layer to an element surface at the high doping layer side, and the thickness of the high doping layer is 15 nm to 1.5 μm, and the maximum doping density in the high doping layer is 1×10 20 cm -3 to 2×10 21 cm -3 . COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题为了抑制在元件前表面附近存在存在的有缺陷的核的堆垛层错及其面积放大率作为起点，从而抑制正向电压的增加，在碳化硅具有台面结构的双极半导体器件。解决方案：碳化硅双极型半导体器件按以下顺序层叠：第一导电型碳化硅单晶衬底; 第一导电型碳化硅漂移层; 第二导电型碳化硅电荷注入层; 以及掺杂浓度高于碳化硅电荷注入层的掺杂密度的第二导电型高掺杂层。该器件的特征还在于，提供从碳化硅漂移层到高掺杂层侧的元件表面的台面结构，并且高掺杂层的厚度为15nm至1.5μm，并且最大掺杂密度在高掺杂层中是1×10 30 / SP 3至2×10 30 / SP 3。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2005311348A Bipolar semiconductor device and process for producing the same 有权
标题翻译：双极半导体器件及其制造方法
公开(公告)号：JP2005311348A
公开(公告)日：2005-11-04
申请号：JP2005089227
申请日：2005-03-25
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： NAKAYAMA KOJI , SUGAWARA YOSHITAKA , TSUCHIDA SHUICHI , KAMATA ISAO , MITSUYANAGI TOSHIYUKI , NAKAMURA TOMONOBU
IPC分类号： H01L21/20 , H01L29/861
摘要： PROBLEM TO BE SOLVED: To provide a bipolar semiconductor device, adapted to reduce propagation of a basal plane dislocation to an epitaxial layer from an SiC single crystal substrate, thereby holding back temporal voltage deterioration in a forward direction, and also to provide a process for producing the bipolar semiconductor device.
SOLUTION: When producing the bipolar semiconductor device formed of a silicon carbide epitaxial layer 2, grown from the surface of a silicon carbide substrate 1, at least a part of the region where electrons and positive holes recombine during applying of electric current, the surface of the silicon carbide substrate 1 is treated with hydrogen etching, and then silicon carbide is epitaxially grown from the treated surface to result in formation of the epitaxial layer 2. The surface of the silicon carbide substrate 1 is treated with chemical mechanical polishing and is then treated with hydrogen polishing, thereby further reducing the propagation of the basal plane dislocation to the epitaxial layer.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种双极半导体器件，适用于减少从SiC单晶衬底向基底面位错到外延层的传播，从而阻止向前方向的时间电压劣化，并且还提供一种制造双极半导体器件的方法。解决方案：当制造由碳化硅衬底1的表面生长的由碳化硅外延层2形成的双极半导体器件时，在施加电流期间电子和正空穴复合的区域的至少一部分，用氢蚀刻处理碳化硅衬底1的表面，然后从处理表面外延生长碳化硅，形成外延层2.碳化硅衬底1的表面用化学机械抛光处理，然后用氢抛光处理，从而进一步减少基面平面位错到外延层的传播。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2008211171A Bipolar semiconductor device, method for manufacturing the same and method for controlling zener voltage 有权
标题翻译：双极半导体器件，其制造方法和控制ZENER电压的方法
公开(公告)号：JP2008211171A
公开(公告)日：2008-09-11
申请号：JP2007306297
申请日：2007-11-27
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： ISHII RYUSUKE , NAKAYAMA KOJI , SUGAWARA YOSHITAKA , TSUCHIDA SHUICHI
IPC分类号： H01L29/866 , H01L29/861
CPC分类号： H01L29/866 , H01L29/06 , H01L29/0615 , H01L29/1608 , H01L29/36 , H01L29/66106 , H01L29/8613
摘要： PROBLEM TO BE SOLVED: To provide a bipolar semiconductor device having high Zener voltage accuracy within a wide Zener voltage range (for instance 10-500 V). SOLUTION: Provided is the bipolar semiconductor device having a mesa structure. In the bipolar semiconductor device, a first conductivity type silicon carbide single crystal substrate, a first conductivity type silicon carbide conductive layer, a second conductivity type heavily doped layer and a second conductivity type silicon carbide conductive layer are laminated in this order. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供在宽齐纳电压范围（例如10-500V）内具有高齐纳电压精度的双极半导体器件。解决方案：提供具有台面结构的双极型半导体器件。在双极型半导体器件中，依次层叠第一导电型碳化硅单晶衬底，第一导电型碳化硅导电层，第二导电型重掺杂层和第二导电型碳化硅导电层。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2006295061A Bipolar semiconductor device, method for recovering forward voltage thereof, and method for reducing stacking fault 有权
标题翻译：双极半导体器件，用于恢复其前向电压的方法以及用于减少堆叠故障的方法
公开(公告)号：JP2006295061A
公开(公告)日：2006-10-26
申请号：JP2005117176
申请日：2005-04-14
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： MITSUYANAGI TOSHIYUKI , TSUCHIDA SHUICHI , KAMATA ISAO , SUGAWARA YOSHITAKA , NAKAYAMA KOJI , ISHII RYUSUKE
IPC分类号： H01L21/324 , H01L21/331 , H01L29/12 , H01L29/73 , H01L29/744 , H01L29/78 , H01L29/861
摘要： PROBLEM TO BE SOLVED: To provide a method for reducing a stacking fault area enlarged by current energization and recovering an increased forward voltage of a silicon carbide bipolar semiconductor device, in the bipolar semiconductor device in which electrons are recoupled to holes upon energization in a silicon carbide epitaxial film grown from a surface of a silicon carbide monocrystal substrate.
SOLUTION: The stacking fault area is enlarged by current energization and the silicon carbide bipolar semiconductor device of the increased forward voltage is heated at a temperature of 350°C or more to recover stacking faults.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种通过电流通电而减小堆积故障区域的方法，并且在双极半导体器件中恢复碳化硅双极型半导体器件的正向电压的增加的方法，其中电子在通电时被重新耦合到孔中在从碳化硅单晶衬底的表面生长的碳化硅外延膜中。解决方案：通过电流通电扩大堆垛层错区域，提高正向电压的碳化硅双极型半导体装置在350℃以上的温度下加热，以回收堆垛层错。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2012033618A Bipolar semiconductor element 审中-公开
标题翻译：双极半导体元件
公开(公告)号：JP2012033618A
公开(公告)日：2012-02-16
申请号：JP2010170617
申请日：2010-07-29
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： NAKAYAMA KOJI , ASANO KATSUNORI , TSUCHIDA SHUICHI , MIYAZAWA TETSUYA
IPC分类号： H01L29/861 , H01L21/205 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/12 , H01L29/15 , H01L29/732 , H01L29/739 , H01L29/744 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a bipolar semiconductor element capable of keeping a forward voltage low by reducing a stress at an interface between a drift layer and a layer adjacent to the drift layer.SOLUTION: In a pin diode 20, each of upper limits of the impurity concentration of an n-type SiC buffer layer 22: (5×10cm); (7×10cm); and (10×10cm), is set corresponding to each of regions of the film thickness of an n-type SiC drift layer 23: (300 μm or less and more than 200 μm); (200 μm or less and more than 100 μm); and (100 μm or less and more than 50 μm), respectively. This can reduce a stress at an interface between the n-type SiC drift layer 23 and the n-type SiC buffer layer 22, so that a forward voltage can be reduced.
摘要翻译：要解决的问题：提供一种能够通过减小漂移层和与漂移层相邻的层之间的界面处的应力而能够保持正向电压低的双极半导体元件。解决方案：在pin二极管20中，n型SiC缓冲层22的杂质浓度的上限中的每一个：（5×10 17 cm - 3 ）; （7×10 17 cm - 3 ）; 和对应于n值的膜厚度的每个区域设置（10×10 17 cm > 3 ）” SiC漂移层23（300μm以下且大于200μm）; （200μm以下且大于100μm）; 和（100μm以下且大于50μm）。这可以降低n型SiC漂移层23和n型SiC缓冲层22之间的界面处的应力，从而可以减小正向电压。版权所有（C）2012，JPO＆INPIT

8. 发明专利

JP2008277396A Silicon carbide zener diode 有权
标题翻译：硅碳化锌二极管
公开(公告)号：JP2008277396A
公开(公告)日：2008-11-13
申请号：JP2007116736
申请日：2007-04-26
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： ISHII RYUSUKE , NAKAYAMA KOJI , SUGAWARA YOSHITAKA , TSUCHIDA SHUICHI
IPC分类号： H01L29/866 , H01L29/06 , H01L29/861
CPC分类号： H01L29/866 , H01L29/0615 , H01L29/1608 , H01L29/66106
摘要： PROBLEM TO BE SOLVED: To provide a mesa type silicon carbide Zener diode that has a large current capacity, without the concentration of electric field in the mesa end of the p-n junction interface. SOLUTION: The silicon carbide Zener diode is a bipolar semiconductor device, having mesa structure wherein a first conductive silicon carbide conductive layer is formed on a first conductive silicon carbide single-crystal substrate and a second conductive silicon carbide conductive layer is formed on the first conductive silicon carbide conductive layer. When reverse voltage is applied, a depletion layer that is formed at the junction interface between the first and second silicon carbide conductive layers does not reach a mesa corner, formed in the first conductive silicon carbide conductive layer. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供具有大电流容量的台面型碳化硅齐纳二极管，而不会在p-n结界面的台面末端产生电场的浓度。解决方案：碳化硅齐纳二极管是具有台面结构的双极半导体器件，其中第一导电碳化硅导电层形成在第一导电碳化硅单晶衬底上，第二导电碳化硅导电层形成在第一导电碳化硅导电层。当施加反向电压时，在第一和第二碳化硅导电层之间的接合界面处形成的耗尽层不会形成在第一导电碳化硅导电层中形成的台面角。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2007165604A Silicon carbide bipolar semiconductor device 有权
标题翻译：碳化硅双极半导体器件
公开(公告)号：JP2007165604A
公开(公告)日：2007-06-28
申请号：JP2005360245
申请日：2005-12-14
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： ISHII RYUSUKE , NAKAYAMA KOJI , SUGAWARA YOSHITAKA , MITSUYANAGI TOSHIYUKI , TSUCHIDA SHUICHI , KAMATA ISAO , NAKAMURA TOMONOBU
IPC分类号： H01L29/861 , H01L21/28 , H01L29/417
CPC分类号： H01L29/1604 , H01L21/0465 , H01L21/047 , H01L29/0615 , H01L29/0619 , H01L29/0661 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/8613
摘要： PROBLEM TO BE SOLVED: To suppress the generation of lamination defects and the area extension thereof in an SiC bipolar semiconductor device having a mesa-type shape, and obtained by growing epitaxially a first-conductivity SiC drift layer and a second-conductivity SiC charge injecting layer on the surface of an SiC single-crystal substrate, to suppress thereby the increase of its forward voltage, and further, to improve its withstanding voltage performance generated when applying a reversed voltage to it.
SOLUTION: On mesa walls or on both mesa walls and mesa peripheries of the SiC bipolar semiconductor device, there are formed degradation preventing layers due to conduction for separating spatially from each other the surfaces of both the mesa walls and mesa peripheral portions and its pn-junction interface. In an aspect, the degradation preventing layers due to conduction comprise second-conductivity silicon carbide low-resistance layers which are brought into equipotential layers when applying a reversed voltage to it. In another aspect, the degradation preventing layers due to conduction comprise second-conductivity silicon carbide conductive layers having metal films formed on their surfaces which are brought into equipotential films when applying a reversed voltage to it. In further another aspect, the degradation preventing layers due to conduction comprise high-resistance amorphous layers.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了抑制在具有台面形状的SiC双极型半导体器件中产生层叠缺陷及其面积扩大，并且通过外延生长第一导电性SiC漂移层和第二导电性 SiC电荷注入层，从而抑制其正向电压的增加，并且进一步提高对其施加反向电压时产生的耐受电压性能。解决方案：在SiC双极半导体器件的台面壁或台面壁和台面周边上，形成由于导电而导致的防锈层，以便在台面壁和台面周边部分的两个表面之间空间分离，其pn结界面。一方面，由于导电而导致的防止降解层包括第二导电性碳化硅低电阻层，当向其施加反向电压时，其被引入等电位层。另一方面，由于导电而导致的防止降解层包括在其表面上形成有金属膜的第二导电性碳化硅导电层，当向其施加反向电压时，其被引入等电位膜。在另一方面，由于传导而导致的防止降解层包括高电阻非晶层。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2007027630A Bipolar semiconductor device and its manufacturing method 审中-公开
标题翻译：双极半导体器件及其制造方法
公开(公告)号：JP2007027630A
公开(公告)日：2007-02-01
申请号：JP2005211296
申请日：2005-07-21
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： MITSUYANAGI TOSHIYUKI , TSUCHIDA SHUICHI , KAMATA ISAO , SUGAWARA YOSHITAKA , NAKAYAMA KOJI , ISHII RYUSUKE
IPC分类号： H01L29/861 , H01L21/336 , H01L29/161 , H01L29/739 , H01L29/74 , H01L29/744 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To suppress generation of lamination defects and the enlargement of area of lamination defect which are generated by continuing the supply of electric power, in a silicon carbide bipolar semiconductor device.
SOLUTION: A surface layer 4, at least high in seed defect density, is removed in a first conductive silicon carbide epitaxial film 2 grown from the front surface of the first conductive silicon carbide single crystal substrate 1 by chemical vapor deposition method, and thereafter, a second conductive silicon carbide epitaxial film 3 is made to grow from the front surface of the silicon carbide epitaxial film 2, whose surface layer 4 is removed. Furthermore, after the second conductive silicon carbide epitaxial film 3 is grown, a surface layer 6 high at least in the seed defect density is removed in the second conductive silicon carbide epitaxial film 3.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：在碳化硅双极型半导体器件中，抑制通过继续供电而产生的层叠缺陷的产生和叠层缺陷的面积的扩大。解决方案：通过化学气相沉积法从第一导电碳化硅单晶衬底1的表面生长的第一导电碳化硅外延膜2中去除至少具有至少高的种子缺陷密度的表面层4，之后，使第二导电性碳化硅外延膜3从除去表面层4的碳化硅外延膜2的前表面生长。此外，在第二导电碳化硅外延膜3生长之后，在第二导电碳化硅外延膜3中除去至少晶种缺陷密度高的表面层6。（C）2007，JPO＆INPIT

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