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1. 发明专利

JP2006295061A Bipolar semiconductor device, method for recovering forward voltage thereof, and method for reducing stacking fault 有权
标题翻译：双极半导体器件，用于恢复其前向电压的方法以及用于减少堆叠故障的方法
公开(公告)号：JP2006295061A
公开(公告)日：2006-10-26
申请号：JP2005117176
申请日：2005-04-14
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： MITSUYANAGI TOSHIYUKI , TSUCHIDA SHUICHI , KAMATA ISAO , SUGAWARA YOSHITAKA , NAKAYAMA KOJI , ISHII RYUSUKE
IPC分类号： H01L21/324 , H01L21/331 , H01L29/12 , H01L29/73 , H01L29/744 , H01L29/78 , H01L29/861
摘要： PROBLEM TO BE SOLVED: To provide a method for reducing a stacking fault area enlarged by current energization and recovering an increased forward voltage of a silicon carbide bipolar semiconductor device, in the bipolar semiconductor device in which electrons are recoupled to holes upon energization in a silicon carbide epitaxial film grown from a surface of a silicon carbide monocrystal substrate.
SOLUTION: The stacking fault area is enlarged by current energization and the silicon carbide bipolar semiconductor device of the increased forward voltage is heated at a temperature of 350°C or more to recover stacking faults.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种通过电流通电而减小堆积故障区域的方法，并且在双极半导体器件中恢复碳化硅双极型半导体器件的正向电压的增加的方法，其中电子在通电时被重新耦合到孔中在从碳化硅单晶衬底的表面生长的碳化硅外延膜中。解决方案：通过电流通电扩大堆垛层错区域，提高正向电压的碳化硅双极型半导体装置在350℃以上的温度下加热，以回收堆垛层错。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2009010120A Silicon carbide bipolar semiconductor device 有权
标题翻译：碳化硅双极半导体器件
公开(公告)号：JP2009010120A
公开(公告)日：2009-01-15
申请号：JP2007169263
申请日：2007-06-27
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： MITSUYANAGI TOSHIYUKI , TSUCHIDA SHUICHI , KAMATA ISAO , ISHII RYUSUKE , NAKAYAMA KOJI , SUGAWARA YOSHITAKA
IPC分类号： H01L29/861 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/12 , H01L29/732 , H01L29/739 , H01L29/744 , H01L29/78
CPC分类号： H01L2224/32245 , H01L2224/45124 , H01L2224/48247 , H01L2924/12032 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To suppress a stacking fault and an area magnification thereof which make a defective nucleus existing near a front surface of an element as a starting point, and thereby to suppress an increase in forward voltage, in a silicon carbide bipolar semiconductor device with a mesa structure. SOLUTION: The silicon carbide bipolar semiconductor device is constituted by laminating the following in order: a first conductivity-type silicon carbide single crystal substrate; a first conductivity-type silicon carbide drift layer; a second conductivity-type silicon carbide charge injection layer; and a second conductivity-type high doping layer with a doping density higher than that of the silicon carbide charge injection layer. This device is also characterized in that there is provided the mesa structure from the silicon carbide drift layer to an element surface at the high doping layer side, and the thickness of the high doping layer is 15 nm to 1.5 μm, and the maximum doping density in the high doping layer is 1×10 20 cm -3 to 2×10 21 cm -3 . COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题为了抑制在元件前表面附近存在存在的有缺陷的核的堆垛层错及其面积放大率作为起点，从而抑制正向电压的增加，在碳化硅具有台面结构的双极半导体器件。解决方案：碳化硅双极型半导体器件按以下顺序层叠：第一导电型碳化硅单晶衬底; 第一导电型碳化硅漂移层; 第二导电型碳化硅电荷注入层; 以及掺杂浓度高于碳化硅电荷注入层的掺杂密度的第二导电型高掺杂层。该器件的特征还在于，提供从碳化硅漂移层到高掺杂层侧的元件表面的台面结构，并且高掺杂层的厚度为15nm至1.5μm，并且最大掺杂密度在高掺杂层中是1×10 30 / SP 3至2×10 30 / SP 3。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2005311348A Bipolar semiconductor device and process for producing the same 有权
标题翻译：双极半导体器件及其制造方法
公开(公告)号：JP2005311348A
公开(公告)日：2005-11-04
申请号：JP2005089227
申请日：2005-03-25
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： NAKAYAMA KOJI , SUGAWARA YOSHITAKA , TSUCHIDA SHUICHI , KAMATA ISAO , MITSUYANAGI TOSHIYUKI , NAKAMURA TOMONOBU
IPC分类号： H01L21/20 , H01L29/861
摘要： PROBLEM TO BE SOLVED: To provide a bipolar semiconductor device, adapted to reduce propagation of a basal plane dislocation to an epitaxial layer from an SiC single crystal substrate, thereby holding back temporal voltage deterioration in a forward direction, and also to provide a process for producing the bipolar semiconductor device.
SOLUTION: When producing the bipolar semiconductor device formed of a silicon carbide epitaxial layer 2, grown from the surface of a silicon carbide substrate 1, at least a part of the region where electrons and positive holes recombine during applying of electric current, the surface of the silicon carbide substrate 1 is treated with hydrogen etching, and then silicon carbide is epitaxially grown from the treated surface to result in formation of the epitaxial layer 2. The surface of the silicon carbide substrate 1 is treated with chemical mechanical polishing and is then treated with hydrogen polishing, thereby further reducing the propagation of the basal plane dislocation to the epitaxial layer.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种双极半导体器件，适用于减少从SiC单晶衬底向基底面位错到外延层的传播，从而阻止向前方向的时间电压劣化，并且还提供一种制造双极半导体器件的方法。解决方案：当制造由碳化硅衬底1的表面生长的由碳化硅外延层2形成的双极半导体器件时，在施加电流期间电子和正空穴复合的区域的至少一部分，用氢蚀刻处理碳化硅衬底1的表面，然后从处理表面外延生长碳化硅，形成外延层2.碳化硅衬底1的表面用化学机械抛光处理，然后用氢抛光处理，从而进一步减少基面平面位错到外延层的传播。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2005167035A Silicon carbide semiconductor device and manufacturing method thereof 审中-公开
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2005167035A
公开(公告)日：2005-06-23
申请号：JP2003405259
申请日：2003-12-03
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： NAKAYAMA KOJI , SUGAWARA YOSHITAKA , ASANO KATSUNORI , TSUCHIDA SHUICHI , KAMATA ISAO , MITSUYANAGI TOSHIYUKI , NAKAMURA TOMONOBU
IPC分类号： H01L21/331 , H01L21/04 , H01L21/329 , H01L21/336 , H01L29/04 , H01L29/12 , H01L29/24 , H01L29/73 , H01L29/739 , H01L29/78 , H01L29/861
CPC分类号： H01L29/868 , H01L29/045 , H01L29/0619 , H01L29/1608 , H01L29/66068 , H01L29/73 , H01L29/7397
摘要： PROBLEM TO BE SOLVED: To prevent the increase of a forward voltage due to aging of a bipolar semiconductor device using a silicon carbide semiconductor.
SOLUTION: The plane having an off-angle θ as 8° with respect to the (000-1) carbon plane of a silicon carbide semiconductor crystal is made to be a growth plane of crystal. A buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on this growth plane with an increase speed of the film thickness per hour (h) which is not less than 3 times larger than that in the prior art, i.e. with film formation speed of 10 μm/h. The flow rate of the raw material gases, which are silane, propane, and a dopant gas are greatly increased to increase the film formation speed.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了防止由于使用碳化硅半导体的双极性半导体器件的老化引起的正向电压的增加。解决方案：将具有相对于碳化硅半导体晶体的（000-1）碳平面的偏角θ为8°的平面制成晶体的生长平面。在该生长平面上形成缓冲层，漂移层和其他p型和n型半导体层，每小时（h）的膜厚度的增加速度不小于先前的3倍即成膜速度为10μm/ h。作为硅烷，丙烷和掺杂剂气体的原料气体的流量大大增加以提高成膜速度。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2007165604A Silicon carbide bipolar semiconductor device 有权
标题翻译：碳化硅双极半导体器件
公开(公告)号：JP2007165604A
公开(公告)日：2007-06-28
申请号：JP2005360245
申请日：2005-12-14
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： ISHII RYUSUKE , NAKAYAMA KOJI , SUGAWARA YOSHITAKA , MITSUYANAGI TOSHIYUKI , TSUCHIDA SHUICHI , KAMATA ISAO , NAKAMURA TOMONOBU
IPC分类号： H01L29/861 , H01L21/28 , H01L29/417
CPC分类号： H01L29/1604 , H01L21/0465 , H01L21/047 , H01L29/0615 , H01L29/0619 , H01L29/0661 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/8613
摘要： PROBLEM TO BE SOLVED: To suppress the generation of lamination defects and the area extension thereof in an SiC bipolar semiconductor device having a mesa-type shape, and obtained by growing epitaxially a first-conductivity SiC drift layer and a second-conductivity SiC charge injecting layer on the surface of an SiC single-crystal substrate, to suppress thereby the increase of its forward voltage, and further, to improve its withstanding voltage performance generated when applying a reversed voltage to it.
SOLUTION: On mesa walls or on both mesa walls and mesa peripheries of the SiC bipolar semiconductor device, there are formed degradation preventing layers due to conduction for separating spatially from each other the surfaces of both the mesa walls and mesa peripheral portions and its pn-junction interface. In an aspect, the degradation preventing layers due to conduction comprise second-conductivity silicon carbide low-resistance layers which are brought into equipotential layers when applying a reversed voltage to it. In another aspect, the degradation preventing layers due to conduction comprise second-conductivity silicon carbide conductive layers having metal films formed on their surfaces which are brought into equipotential films when applying a reversed voltage to it. In further another aspect, the degradation preventing layers due to conduction comprise high-resistance amorphous layers.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了抑制在具有台面形状的SiC双极型半导体器件中产生层叠缺陷及其面积扩大，并且通过外延生长第一导电性SiC漂移层和第二导电性 SiC电荷注入层，从而抑制其正向电压的增加，并且进一步提高对其施加反向电压时产生的耐受电压性能。解决方案：在SiC双极半导体器件的台面壁或台面壁和台面周边上，形成由于导电而导致的防锈层，以便在台面壁和台面周边部分的两个表面之间空间分离，其pn结界面。一方面，由于导电而导致的防止降解层包括第二导电性碳化硅低电阻层，当向其施加反向电压时，其被引入等电位层。另一方面，由于导电而导致的防止降解层包括在其表面上形成有金属膜的第二导电性碳化硅导电层，当向其施加反向电压时，其被引入等电位膜。在另一方面，由于传导而导致的防止降解层包括高电阻非晶层。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2007027630A Bipolar semiconductor device and its manufacturing method 审中-公开
标题翻译：双极半导体器件及其制造方法
公开(公告)号：JP2007027630A
公开(公告)日：2007-02-01
申请号：JP2005211296
申请日：2005-07-21
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： MITSUYANAGI TOSHIYUKI , TSUCHIDA SHUICHI , KAMATA ISAO , SUGAWARA YOSHITAKA , NAKAYAMA KOJI , ISHII RYUSUKE
IPC分类号： H01L29/861 , H01L21/336 , H01L29/161 , H01L29/739 , H01L29/74 , H01L29/744 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To suppress generation of lamination defects and the enlargement of area of lamination defect which are generated by continuing the supply of electric power, in a silicon carbide bipolar semiconductor device.
SOLUTION: A surface layer 4, at least high in seed defect density, is removed in a first conductive silicon carbide epitaxial film 2 grown from the front surface of the first conductive silicon carbide single crystal substrate 1 by chemical vapor deposition method, and thereafter, a second conductive silicon carbide epitaxial film 3 is made to grow from the front surface of the silicon carbide epitaxial film 2, whose surface layer 4 is removed. Furthermore, after the second conductive silicon carbide epitaxial film 3 is grown, a surface layer 6 high at least in the seed defect density is removed in the second conductive silicon carbide epitaxial film 3.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：在碳化硅双极型半导体器件中，抑制通过继续供电而产生的层叠缺陷的产生和叠层缺陷的面积的扩大。解决方案：通过化学气相沉积法从第一导电碳化硅单晶衬底1的表面生长的第一导电碳化硅外延膜2中去除至少具有至少高的种子缺陷密度的表面层4，之后，使第二导电性碳化硅外延膜3从除去表面层4的碳化硅外延膜2的前表面生长。此外，在第二导电碳化硅外延膜3生长之后，在第二导电碳化硅外延膜3中除去至少晶种缺陷密度高的表面层6。（C）2007，JPO＆INPIT

7. 发明专利

JP2006237125A Method of operating bipolar type semiconductor device, and bipolar type semiconductor device 审中-公开
标题翻译：双极型半导体器件的操作方法和双极型半导体器件
公开(公告)号：JP2006237125A
公开(公告)日：2006-09-07
申请号：JP2005046850
申请日：2005-02-23
申请人： Central Res Inst Of Electric Power Ind , Kansai Electric Power Co Inc:The , 財団法人電力中央研究所 , 関西電力株式会社
发明人： SUGAWARA YOSHITAKA , NAKAYAMA KOJI , ISHII RYUSUKE , MITSUYANAGI TOSHIYUKI , TSUCHIDA SHUICHI , KAMATA ISAO
IPC分类号： H01L29/861 , H01L21/329
摘要： PROBLEM TO BE SOLVED: To suppress the increase of a created stacking fault area by continuing energizing in a bipolar type semiconductor device which performs electron and hole recombination in the time of energization inside a silicon carbide epitaxial film grown up from the front surface of a silicon carbide single crystal substrate.
SOLUTION: A conducting operation is performed while the above SiC bipolar type semiconductor device is maintained in a temperature environment at 350°C or more.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了通过在从前表面生长的碳化硅外延膜内的通电时进行电子和空穴复合的双极型半导体器件中继续通电来抑制产生的堆垛层错区域的增加的碳化硅单晶基板。解决方案：在上述SiC双极型半导体器件保持在350℃以上的温度环境下进行导通操作。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2007318031A Manufacturing method of silicon carbide semiconductor element 有权
标题翻译：碳化硅半导体元件的制造方法
公开(公告)号：JP2007318031A
公开(公告)日：2007-12-06
申请号：JP2006148566
申请日：2006-05-29
申请人： Central Res Inst Of Electric Power Ind , 財団法人電力中央研究所
发明人： TSUCHIDA SHUICHI , KAMATA ISAO , MITSUYANAGI TOSHIYUKI , LIUTAURAS STORASTA
IPC分类号： H01L21/66 , H01L21/336 , H01L29/12 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To manufacture a silicon carbide semiconductor element without any influence to element characteristics due to crystal defects by specifying the positions of dislocation and lamination defects in a wafer surface, and their types.
SOLUTION: The positions of the dislocation and lamination defects in the wafer surface, and their types are acquired from emission mapping data obtained by scanning the inside of the wafer surface for each collective measurement region in which luminous images are detected collectively by a two-dimensional CCD array. Based on the information, the semiconductor element after cutting/separation from the wafer is screened. In another embodiment, the formation position of each semiconductor element in the wafer surface is determined based on the information so that dislocation and lamination defects are avoided. Further, in another embodiment, processing for adding a structure is performed, where the structure is used to inactivate a part where the lamination defects are present to reduce influence to the element characteristics of the part.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过指定晶片表面中的位错和层叠缺陷的位置以及它们的类型，制造碳化硅半导体元件而不会由于晶体缺陷而对元件特性没有任何影响。解决方案：晶片表面中的位错和层叠缺陷的位置及其类型是从通过扫描由晶片表面的内部获得的每个集合测量区域获得的发射映射数据获取的，其中发光图像被集体检测二维CCD阵列。基于该信息，对从晶片进行切割/分离后的半导体元件进行筛选。在另一个实施例中，基于该信息确定晶片表面中的每个半导体元件的形成位置，从而避免位错和层叠缺陷。此外，在另一个实施例中，进行用于添加结构的处理，其中使用结构来使存在层叠缺陷的部分失活以减少对部件的元件特性的影响。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2007318030A Crystal defect inspection method and crystal defect inspection apparatus of silicon carbide single crystal 有权
标题翻译：晶体缺陷检测方法和晶体缺陷检测装置的碳化硅单晶
公开(公告)号：JP2007318030A
公开(公告)日：2007-12-06
申请号：JP2006148565
申请日：2006-05-29
申请人： Central Res Inst Of Electric Power Ind , 財団法人電力中央研究所
发明人： TSUCHIDA SHUICHI , KAMATA ISAO , MITSUYANAGI TOSHIYUKI , LIUTAURAS STORASTA
IPC分类号： H01L21/66 , G01N21/66
摘要： PROBLEM TO BE SOLVED: To provide a crystal defect inspection method and a crystal defect inspection apparatus capable of performing inspection quickly and inexpensively when inspecting the in-plane distribution of dislocation and lamination defects existing in the epitaxial film of a silicon carbide single-crystal wafer for manufacturing a semiconductor element by an electroluminescence method.
SOLUTION: Voltage is applied at an area to the back of a wafer, where the wafer is grounded by pushing out a liquid metal onto the epitaxial film at a measurement position from the tip of a tubular member, or bringing a conductive film electrode that is made to contact and separate from the wafer into contact. Then, the two-dimensional information of EL light from each position corresponding to an array at a collective measurement region in a wafer surface is acquired collectively by the two-dimensional CCD array from the back side of the wafer. Each collective measurement region in the wafer surface is scanned, thus obtaining mapping data related to the EL light in the entire region to be inspected in the wafer surface and specifying the positions of crystal defects in the wafer surface based on the data.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种在检查存在于碳化硅单体的外延膜中的位错和层叠缺陷的面内分布时能够快速且廉价地进行检查的晶体缺陷检查方法和晶体缺陷检查装置用于通过电致发光法制造半导体元件的晶体晶片。解决方案：在晶片背面的一个区域上施加电压，其中通过在管状构件的尖端处的测量位置处将液态金属推出到外延膜上而将晶片接地，或者使导电膜使与晶片接触和分离的电极接触。然后，从晶片的背面通过二维CCD阵列一起获取与晶片表面的集体测量区域中的阵列对应的每个位置的EL光的二维信息。对晶片表面中的每个集体测量区域进行扫描，从而在晶片表面中获得要检查的整个区域中的EL光的映射数据，并基于该数据指定晶片缺陷的位置。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2007220889A Schottky junction semiconductor device and its manufacturing method 审中-公开
标题翻译：肖特接头半导体器件及其制造方法
公开(公告)号：JP2007220889A
公开(公告)日：2007-08-30
申请号：JP2006039358
申请日：2006-02-16
申请人： Central Res Inst Of Electric Power Ind , 財団法人電力中央研究所
发明人： TSUCHIDA SHUICHI , NAKAMURA TOMONOBU , MITSUYANAGI TOSHIYUKI
IPC分类号： H01L29/872 , H01L21/338 , H01L29/47 , H01L29/812
CPC分类号： H01L29/872 , H01L21/0495 , H01L29/045 , H01L29/1608 , H01L29/66143
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide Schottky junction semiconductor device capable of controlling a Schottky barrier height to a desired value, in a range of making a power loss minimum without increasing n-factors while using a Ta electrode as a Schottky electrode, and its manufacturing method.
SOLUTION: Ta is deposited on a crystal face of an n-type silicon carbide epitaxial film, in which an inclined angle from a (000-1) C face is in a range of 0-10°, so as to form the Schottky electrode by executing heat treatment to it in a temperature range of 300-1,200°C after the deposition.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种能够在使用Ta电极时将肖特基势垒高度控制到期望值的碳化硅肖特基结半导体器件，其在不增加n因子的情况下在降低功率损耗的范围内肖特基电极及其制造方法。解决方案：将Ta沉积在n型碳化硅外延膜的晶面上，其中从（000-1）C面的倾斜角在0-10°的范围内，以形成通过在沉积后在300-1200℃的温度范围内对其进行热处理来形成肖特基电极。版权所有（C）2007，JPO＆INPIT

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