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1. 发明专利

JP2007280606A Dram chips 有权
标题翻译： DRAM芯片
公开(公告)号：JP2007280606A
公开(公告)日：2007-10-25
申请号：JP2007183074
申请日：2007-07-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HORIGUCHI SHINJI , NAKAMURA MASAYUKI , OKUMA YOSHIYUKI , KAJITANI KAZUHIKO , NAKAGOME YOSHINOBU
IPC分类号： G11C11/4074 , G11C11/401
摘要： PROBLEM TO BE SOLVED: To especially reduce an active standby current by achieving low power consumption of a power supply circuit of a semiconductor memory. SOLUTION: A DRAM chip is provided with a first voltage supply means for supplying a first voltage to a plurality of sense amplifiers and a second voltage supply means for supplying a second voltage to a column decoder. The first voltage supply means includes a plurality of first voltage limiter circuits arranged in the number same as the number of plurality of memory banks correspondingly to each of the memory banks and a second voltage limiter circuit whose current supply capability is smaller than that of the first voltage limiter circuit. The second voltage supply means includes: a third voltage limiter circuit; a fourth voltage limiter circuit whose current supply capability is smaller than that of the third voltage limiter circuit and whose output node is connected to the output node of the third voltage limiter circuit; and a fifth voltage limiter circuit whose current supply capability is smaller than that of the third voltage limiter circuit and whose output node is connected to the output nodes of the third and fourth voltage limiter circuits. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过实现半导体存储器的电源电路的低功耗来特别地降低主动待机电流。解决方案：DRAM芯片设置有用于向多个读出放大器提供第一电压的第一电压供应装置和用于向列解码器提供第二电压的第二电压供应装置。第一电压供给装置包括多个与每个存储体相对应的多个存储体的数量相同的第一限压器电路;以及第二限压器电路，其电流供应能力小于第一限压电路。第二电压供给装置包括：第三限压器电路; 第四限压电路，其电流供给能力小于第三限压电路，其输出节点连接到第三限压电路的输出节点; 以及电流供给能力小于第三限压电路的第五限压电路，其输出节点连接到第三和第四限压器电路的输出节点。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2004259431A Dram 有权
公开(公告)号：JP2004259431A
公开(公告)日：2004-09-16
申请号：JP2004112616
申请日：2004-04-07
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HORIGUCHI SHINJI , NAKAMURA MASAYUKI , OKUMA YOSHIYUKI , KAJITANI KAZUHIKO , NAKAGOME YOSHINOBU
IPC分类号： G11C11/407 , G11C11/401
摘要： PROBLEM TO BE SOLVED: To reduce the electric power consumption of the power source circuit of a semiconductor memory, and more particularly, to reduce the standby current thereof. SOLUTION: A DRAM (dynamic RAM) is equipped with a plurality of memory banks which can be activated by respective activation commands and a plurality of power supply circuits which are disposed in corresponding to the respective memory banks, respectively receive external power supply voltages and output internal power supply voltages. The outputs of the power supply circuits are respectively connected to the corresponding memory banks and turn on the power source circuit component in correspondence to one of the memory banks among the power source circuits in response with the command for activating the memory bank and turn off the remaining power source circuits. COPYRIGHT: (C)2004,JPO&NCIPI

3. 发明专利

JP2004213895A Semiconductor device 有权
公开(公告)号：JP2004213895A
公开(公告)日：2004-07-29
申请号：JP2004112617
申请日：2004-04-07
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HORIGUCHI SHINJI , NAKAMURA MASAYUKI , OKUMA YOSHIYUKI , KAJITANI KAZUHIKO , NAKAGOME YOSHINOBU
IPC分类号： G11C11/401 , G11C11/407
摘要： PROBLEM TO BE SOLVED: To reduce power consumption of a power supply circuit of a semiconductor memory and to reduce an active standby current in particular.
SOLUTION: A plurality of memory banks that can be respectively and independently activated by an activation command and a plurality of power supply circuits provided respectively corresponding to the memory banks to respectively receive external power source voltage and output a prescribed internal power source voltage are provided. Outputs of the power supply circuits are respectively connected to corresponding memory banks, a power supply circuit provided in accordance with a corresponding bank among the power supply circuits are turned on in a response to a command for activating one of the memory banks, and the other power supply circuits are turned off.
COPYRIGHT: (C)2004,JPO&NCIPI

4. 发明专利

JP2004055130A Semiconductor device 有权
公开(公告)号：JP2004055130A
公开(公告)日：2004-02-19
申请号：JP2003200842
申请日：2003-07-24
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKAGOME YOSHINOBU , TACHIBANA MASARU
IPC分类号： G11C11/41 , G11C11/401 , G11C11/413 , H01L21/8244 , H01L27/11
摘要： PROBLEM TO BE SOLVED: To provide a high integrated multi-port RAM which can perform simultaneous and parallel read / write from a plurality of ports practically. SOLUTION: The multi-port RAM is provided with a plurality of memory blocks (MB(i, J)) by the memory cell of a single port, the global bit lines (GBLa, GBLaB, GBLb and GBLbB) of multi-port constitution and a switch means (SW(i, j)) for selectively connecting a bit line inside the memory block to the global bit line. The global bit lines and the bit lines are provided in different wiring layers and the wiring pitch of the global bit lines is made larger than the wiring pitch of the bit lines. COPYRIGHT: (C)2004,JPO

5. 发明专利

JP2003179483A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003179483A
公开(公告)日：2003-06-27
申请号：JP2002229399
申请日：2002-08-07
申请人： HITACHI LTD
发明人： NAKAGOME YOSHINOBU , ITO KIYOO
IPC分类号： G11C11/413 , G11C11/407 , G11C11/408 , H01L21/822 , H01L27/04 , H03K19/00 , H03K19/0175 , H03K19/0185
摘要： PROBLEM TO BE SOLVED: To realize high-speed operation of a semiconductor device operating on a low voltage and low power consumption at the same time. SOLUTION: The semiconductor device comprises a first circuit block having a PMOS (T 35 in Fig. 28) and a first operating state, and a second circuit block having an NMOS (T116 in Fig. 40). The PMOS has the characteristics in which when a first board bias potential is applied in the first operating state and a voltage between the gate and the source (GS) is set to 0 V, a first current larger than a current regarded as to be substantially zero in the circuit operation flows to the source and drain (SD) route and the characteristics, in which when a second board bias potential is applied in the second operating state and a voltage between the G and S is set to 0 V, the current flowing to the SD route becomes smaller than the first current. The NMOS constitutes the semiconductor device, in which its threshold value voltage is larger than that of the PNMOS, and the potential of the source is applied as the board bias potential in the first and second operating states. Accordingly, high-speed operation of the semiconductor device operated at the low voltage and the low power consumption are made compatible. COPYRIGHT: (C)2003,JPO

6. 发明专利

JP2002117674A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002117674A
公开(公告)日：2002-04-19
申请号：JP2000314428
申请日：2000-10-10
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： HORIGUCHI SHINJI , TSUKIMORI AKIFUMI , TACHIBANA RIICHI , NAKAGOME YOSHINOBU
IPC分类号： G11C11/407 , G11C11/401 , G11C11/409
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory in which an interval from a write-in command to a read-out command can be shortened and an effective data transfer rate can be enhanced. SOLUTION: This device is provided with plural address counters and plural timing generating circuits, provided corresponding to each of plural memory banks, a data bus for read-out and a data bus for write-in provided commonly for plural memory banks, a data output buffer connected to the data bus for read-out, and a data input buffer connected to the data bus for write-in.

7. 发明专利

JP2001256175A MEMORY SYSTEM 失效
公开(公告)号：JP2001256175A
公开(公告)日：2001-09-21
申请号：JP2000072483
申请日：2000-03-10
申请人： HITACHI LTD
发明人： SENBA SEIJI , NISHIO YOJI , NAKAGOME YOSHINOBU
IPC分类号： G06F1/18 , G06F12/02 , G06F13/16 , G11C5/04 , G11C5/06 , H05K1/02 , H05K1/14
摘要： PROBLEM TO BE SOLVED: To provide a memory system for suppressing signal reflection on a transmission signal line and enabling high-speed access. SOLUTION: This memory system is provided with a controller (102) capable of controlling a memory operation and memory connectors (104A and 104B) capable of mounting a memory module (1) on a system board (101). The memory module is provided with plural memory chips (11) connected to module data wiring and module power supply wiring. The module data wiring of the respective memory modules is consecutively connected through serial routes (133 and 135) inside the connectors and the individual module data wiring does not constitute branching wiring to system data wiring (107) on the system board. Thus, the signal reflection due to branching from the data wiring on the system board is not generated. Since power is parallelly supplied from the system board through parallel routes (138 and 139) inside the connectors, power supply is stabilized.

8. 发明专利

JP2001250382A CLOCK REPRODUCING CIRCUIT 失效
公开(公告)号：JP2001250382A
公开(公告)日：2001-09-14
申请号：JP2000063326
申请日：2000-03-03
申请人： HITACHI LTD
发明人： OKUDA YUICHI , NAKAGOME YOSHINOBU
IPC分类号： G11C11/407 , G06F1/06 , G11C11/4076 , H03K5/13 , H03K5/131 , H03L7/00 , H03L7/081
摘要： PROBLEM TO BE SOLVED: To provide a DLL lower in current consumption at the time of standby of a system by using an analog DLL low in an operation current is low. SOLUTION: Since a phase error does not exceed a tolerance immediately even if an analog DLL is stopped, the analog DLL is constituted so that the analog DLL is operated intermittently by a standby timing control means 20 at the time of standby. Thereby, current consumption can be reduced which a phase error between a phase of an input clock and a phase of a data output is kept within the tolerance.

9. 发明专利

JP2001244805A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001244805A
公开(公告)日：2001-09-07
申请号：JP2001012613
申请日：2001-01-22
申请人： HITACHI LTD
发明人： NAKAGOME YOSHINOBU , ITO KIYOO , TAKEUCHI MIKI
IPC分类号： H01L21/822 , H01L27/04 , H03K19/0185
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can operate at a low source voltage. SOLUTION: The semiconductor integrated circuit is equipped with a 1st CMOS circuit (INV3) connected to a 1st voltage (VCC-VSS) and outputs a 1st signal having the amplitude of the 1st voltage and a 2nd CMOS circuit (TP6, TP6) which receives the 1st signal at its input node and outputs a 2nd signal having the amplitude of a 2nd voltage; and the threshold voltage of a MOS transistor included in the 2nd CMOS circuit is made lower than the threshold voltage of a MOS transistor included in the 1st CMOS circuit and the 1st voltage in higher than the 2nd voltage.

10. 发明专利

JP2001189078A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2001189078A
公开(公告)日：2001-07-10
申请号：JP2000306775
申请日：2000-10-05
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： SONODA TAKAHIRO , SAKATA TAKESHI , MORITA SADAYUKI , NAKAGOME YOSHINOBU , TADOKORO HARUKO , NAGASHIMA YASUSHI
IPC分类号： G11C11/407
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory in which DQS glidge resistance is improved and which has DDR constitution being easy to use. SOLUTION: This device is a dynamic RAM of which operation of an internal circuit is controlled synchronizing with a clock signal, the device is provided with an input circuit in which plural write-in data inputted in serial corresponding it are taken successively in plural first latch circuits by using a second clock signal inputted at the time of write-in operation, write-in data taken in the first latch circuit is taken in the second latch circuit by using the first clock signal and it is transmitted to an input/output data bus, the third clock signal is formed by providing a logic circuit masking a noise generated at the time of finish of the second clock signal by logic of the first clock and the second clock signals, and it is supplied to the first latch circuit outputting the write-in data to an input of the second latch circuit.

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