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1. 发明专利

JP2008071522A Switching operation device and switching device used for this 有权
标题翻译：切换操作设备和用于此的切换设备
公开(公告)号：JP2008071522A
公开(公告)日：2008-03-27
申请号：JP2006246866
申请日：2006-09-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMAZAKI MIKI , NAKAMURA MASAYUKI , HAYASHI KUNZAN , KOBAYASHI MASAHITO , KIKUKAWA SHUICHI
IPC分类号： H01H33/42
摘要： PROBLEM TO BE SOLVED: To provide a switching operation device and a switching device using the same easy to carry out coupling tuning and an assembly work, and yet, with superb coupling strength of a lever with a shaft.
SOLUTION: The switching operation device 4 for a switch is provided with a rotating shaft 5, a first and a second engagement grooves 18 provided at an outer periphery of the rotating shaft 5 along its axis line direction, a first lever 6 fitted with an engagement protrusion 19 for engagement with the first engagement groove 18 at a base end side, and a second lever 7 fitted with an engagement protrusion for engagement with the second engagement groove 18 at a base end side.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种切换操作装置和使用该切换操作的开关装置，其易于执行联接调谐和组装工作，而且具有杆与杆的极好的联接强度。解决方案：用于开关的切换操作装置4设置有旋转轴5，沿着其轴线方向设置在旋转轴5的外周的第一和第二接合槽18，安装在第一杆6上的第一杆6 具有用于在基端侧与第一接合槽18接合的接合突起19和在基端侧装配有与第二接合槽18接合的接合突起的第二杆7。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2004259442A Semiconductor device 有权
公开(公告)号：JP2004259442A
公开(公告)日：2004-09-16
申请号：JP2004160021
申请日：2004-05-28
申请人： Hitachi Device Eng Co Ltd , Hitachi Ltd , 日立デバイスエンジニアリング株式会社 , 株式会社日立製作所
发明人： TAKAHASHI TSUGIO , KITSUKAWA GORO , AKIBA TAKESADA , KAWASE YASUSHI , NAKAMURA MASAYUKI
IPC分类号： G11C11/401
摘要： PROBLEM TO BE SOLVED: To achieve a dynamic RAM having configuration sufficiently exhibiting an hierarchial structure effect. SOLUTION: A first memory array is constituted by providing a plurality of first memory cells at the intersections of a plurality of first bit lines intersecting a plurality of first sub-word lines corresponding to first main word lines. A second memory array is constituted by providing a plurality of second memory cells at the intersections of a plurality of second bit lines intersecting a plurality of second sub-word lines corresponding to second main word lines. Furthermore, a semiconductor device is provided with: a first and a second sub-common IO line extended in a first direction and connected to the plurality of first bit lines and the plurality of second bit lines, respectively; main IO lines extended in a second direction intersecting the first direction and connected, through a first and a second switch circuit, to the first and the second sub-common IO line; and a first and a second amplifier circuit between the first and the second sub-common IO line and the main IO lines. COPYRIGHT: (C)2004,JPO&NCIPI

3. 发明专利

JP2008186547A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2008186547A
公开(公告)日：2008-08-14
申请号：JP2007020986
申请日：2007-01-31
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： NAKATANI HIROAKI , TAKEMURA RIICHIRO , AKIYAMA SATORU , SEKIGUCHI TOMONORI , NAKAMURA MASAYUKI , MIYATAKE SHINICHI
IPC分类号： G11C11/4091
CPC分类号： G11C11/4091 , G11C7/08 , G11C2207/005
摘要： PROBLEM TO BE SOLVED: To provide technology to control a shared MOS transistor gate voltage that can improve the sensing speed and quickly read data by preventing data inversion due to noise and reducing the bit line capacity when used for the low voltage. SOLUTION: The sensing speed is increased via a gate voltage control circuit of the shared MOS transistor connecting a sense amplifier and a memory cell array by considering the noise at sensing, lowering the shared MOS transistor gate voltage (SHR) in two steps and reducing the amplified bit line capacity. Thus, the column selection signal is quickly started, and the data read time is shortened. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供技术来控制共享的MOS晶体管栅极电压，其可以通过防止由于噪声导致的数据反转并且当用于低电压时降低位线容量来提高感测速度并快速读取数据。解决方案：通过考虑传感噪声连接读出放大器和存储单元阵列的共享MOS晶体管的栅极电压控制电路提高感测速度，分两步降低共享MOS晶体管栅极电压（SHR）并降低放大的位线容量。因此，列选择信号快速启动，数据读取时间缩短。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2008028055A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008028055A
公开(公告)日：2008-02-07
申请号：JP2006197602
申请日：2006-07-20
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： AKIYAMA SATORU , TSUCHIYA RYUTA , SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , NAKAMURA MASAYUKI , YAMAZAKI YASUSHI , SHIRATAKE SHIGERU
IPC分类号： H01L21/8242 , H01L21/3205 , H01L23/52 , H01L27/108
CPC分类号： H01L27/10894 , G11C7/18 , G11C11/404 , G11C11/4097 , H01L27/10876 , H01L27/10891 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a DRAM capable of realizing reduced power consumption, high-speed operation, and high reliability. SOLUTION: The gate electrode 7 of the memory cell transistor of the DRAM is formed of an n-type polycrystalline silicon film 7n and a W film 8 laminated thereon. Part of the polycrystalline silicon film 7n is embedded within the groove 13 formed in the silicon substrate 1 to increase the effective channel length of the memory cell transistor. The other part of the polycrystalline silicon film 7n is projected above the groove 13 and the top face thereof is located above the surface of the silicon substrate 1 (p-type well 3), so that the distances are ensured between the W film 8 and the source, and between the W film 8 and the drain (n-type semiconductor regions 9a, 9b). COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供能够实现降低功耗，高速运行和高可靠性的DRAM。解决方案：DRAM的存储单元晶体管的栅极7由层叠在其上的n型多晶硅膜7n和W膜8形成。多晶硅膜7n的一部分嵌入到形成在硅衬底1中的槽13内，以增加存储单元晶体管的有效沟道长度。多晶硅膜7n的另一部分突出在槽13的上方，其顶面位于硅衬底1（p型阱3）的表面上方，从而确保W膜8与源极，以及W膜8和漏极（n型半导体区域9a，9b）之间。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2005260254A Method for manufacturing semiconductor integrated circuit device 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：JP2005260254A
公开(公告)日：2005-09-22
申请号：JP2005107700
申请日：2005-04-04
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KAJITANI KAZUHIKO , NAKAMURA MASAYUKI , TACHIBANA RIICHI , KITSUKAWA GORO
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To reduce an area occupied by a direct peripheral circuit (sense amplifier, word shunt, etc.) in a large capacity DRAM having a memory cell with a COB (Capacitor Over Bitline) structure. SOLUTION: By electrically connecting an n-channel type MISFETQs in the direct peripheral circuit arranged in close to a memory array and a common source line PN 1 via a pad layer 16 composed of the same conductive film as that of a storage electrode 15 of the memory cell, the aspect ratio of a contact hole 22 formed at the upper part of the pad layer 16 is reduced. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了减小具有具有COB（电容器位线）结构的存储单元的大容量DRAM中的直接外围电路（读出放大器，分流等）所占据的面积。解决方案：通过电连接布置在存储器阵列附近的直接外围电路中的n沟道型MISFETQ和公共源极线PN 1 ，通过由相同导电作为存储单元的存储电极15的薄膜，形成在焊盘层16的上部的接触孔22的纵横比减小。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2007280611A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007280611A
公开(公告)日：2007-10-25
申请号：JP2007201639
申请日：2007-08-02
申请人： Hitachi Display Devices Ltd , Hitachi Ltd , 株式会社日立ディスプレイデバイシズ , 株式会社日立製作所
发明人： TAKAHASHI TSUGIO , KITSUKAWA GORO , AKIBA TAKESADA , KAWASE YASUSHI , NAKAMURA MASAYUKI
IPC分类号： G11C11/401 , G11C11/4096
摘要： PROBLEM TO BE SOLVED: To provide a structure that achieves a full effect of a layered structure of word and common I/O. SOLUTION: A plurality of first (and second) sub-word lines are provided so as to correspond to main word lines. A plurality of first (and second) memory cells are provided at intersecting points of these sub-word lines and a plurality of first (and second) bit lines to configure first (and second) memory arrays. A sub-common I/O line is connected to the plurality of first (and second) bit lines and extends in a first direction. A main I/O line is connected to the sub-common line and extends in a second direction that intersects with the first direction. A plurality of first (and second) switch circuits are provided between each of the plurality of first (and second) bit lines and the sub-common I/O line. An amplifier circuit is provided between the sub-common I/O line and the main I/O line and amplifies a signal transmitted through the sub-common I/O line. The length of the sub-common I/O line is shorter than that of the main I/O line. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供实现字和通用I / O的分层结构的全部效果的结构。解决方案：提供多个第一（和第二）子字线，以便对应于主字线。在这些子字线和多个第一（和第二）位线的交叉点处提供多个第一（和第二）存储器单元，以配置第一（和第二）存储器阵列。子公共I / O线连接到多个第一（和第二）位线并沿第一方向延伸。主I / O线连接到子公共线并沿与第一方向相交的第二方向延伸。在多个第一（和第二）位线和子公共I / O线中的每一个之间提供多个第一（和第二）开关电路。在子公共I / O线和主I / O线之间提供放大器电路，并放大通过子公共I / O线传输的信号。子公共I / O线的长度短于主I / O线的长度。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2005174386A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2005174386A
公开(公告)日：2005-06-30
申请号：JP2003408863
申请日：2003-12-08
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： MORINO MAKOTO , NAKAMURA MASAYUKI
IPC分类号： G11C29/04 , G06F11/10 , G11C7/00 , G11C11/401 , G11C29/00 , G11C29/42
CPC分类号： G06F11/1008 , G11C29/789 , G11C29/802 , G11C29/812
摘要： PROBLEM TO BE SOLVED: To make it possible to perform a correction operation by an ECC circuit without restricting memory access from the outside and also to reduce the number of ECC circuits.
SOLUTION: In the semiconductor integrated circuit device having a memory array having first to Nth (N is the integer of ≥2) banks, the memory array has also first to Nth column system relieving circuit blocks 11c, first to Nth row system relieving circuit blocks 11R, first to Nth ECC phase blocks, first to Nth ECC circuits as redundant blocks for first to N th banks, and error correction is performed respectively for column system relieving phase data of first to Nth column system relieving circuit blocks 11 and for row system relieving phase data of first to Nth row system relieving circuit blocks 11 in first to Nth ECC circuits using first ti Nth ECC phase blocks of ECC phase data during an initial cycle.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：使得可以通过ECC电路执行校正操作而不限制来自外部的存储器访问以及减少ECC电路的数量。解决方案：在具有第一至第N（N为≥2的整数）存储器阵列的半导体集成电路器件中，存储器阵列还具有第一至第N列系统缓解电路块11c，第一至第N行系统解除电路块11R，第一至第N ECC相位块，第一至第N ECC块电路作为第一至第N组的冗余块，并分别执行第一至第N系列缓冲电路块11和用于在初始周期期间使用第一到第N个ECC电路的第一到第N个ECC系统缓冲电路块11的行系统缓和相位数据，使用第一第N个ECC相位数据的第N个ECC相位块。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2000077536A Manufacture of semiconductor device 审中-公开
标题翻译：半导体器件的制造
公开(公告)号：JP2000077536A
公开(公告)日：2000-03-14
申请号：JP24897698
申请日：1998-09-03
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ASAKURA HISAO , TADAKI YOSHITAKA , SEKIGUCHI TOSHIHIRO , NAGAI AKIRA , MIYAMOTO MASABUMI , NAKAMURA MASAYUKI
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/8238 , H01L21/8242 , H01L21/8246 , H01L27/088 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10894 , H01L21/823857 , H01L27/10852 , H01L27/10873 , Y10S438/981
摘要： PROBLEM TO BE SOLVED: To adjust the threshold voltage of a p-channel type field effect transistor and n-channel type field effect transistor with a relatively thin gate insulating film, without increasing the number of photomasks and the number of formation/removal processes for the photoresist pattern.
SOLUTION: Using a photoresist film 3e, which is a mask for etching/ removing a gate insulating film 7a in a formation region of a relatively thin gate insulating film, an impurity for adjusting the threshold voltage of an n- channel type field effect transistor and p-channel type field effect transistor having a relatively thin gate insulating film, is introduced in batch in a semiconductor substrate 1 exposed there.
COPYRIGHT: (C)2000,JPO
摘要翻译：要解决的问题：通过相对薄的栅极绝缘膜来调节p沟道型场效应晶体管和n沟道型场效应晶体管的阈值电压，而不增加光掩模的数量和形成/去除处理的数量光刻胶图案。解决方案：使用作为蚀刻/去除相对薄的栅极绝缘膜的形成区域中的栅极绝缘膜7a的掩模的光致抗蚀剂膜3e，用于调整n沟道型场效应晶体管的阈值电压的杂质，以及在其中暴露的半导体衬底1中分批引入具有相对薄的栅极绝缘膜的p沟道型场效应晶体管。

9. 发明专利

JP2008251070A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2008251070A
公开(公告)日：2008-10-16
申请号：JP2007088693
申请日：2007-03-29
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： TAKEMURA RIICHIRO , SEKIGUCHI TOMONORI , AKIYAMA SATORU , NAKATANI HIROAKI , NAKAMURA MASAYUKI
IPC分类号： G11C11/4076 , G06F1/06 , G11C11/401 , G11C11/407 , H03K5/13
CPC分类号： G11C7/04 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C2207/2272
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which generates a proper inner timing signal according to manufacturing variation, operating voltage variation, and temperature change so as to provide a stable performance in a designated latency and external clock frequency.
SOLUTION: The semiconductor device has: a first delay circuit block which generates a timing signal for a circuit block for working in a column cycle time determined by an external input command cycle; and a second delay circuit block whose total delay is adjusted to a difference between the column cycle time and the access time determined by the external clock and latency. Regarding the delay circuit blocks, the delay of each delay circuit is properly adjusted according to the column latency and operating frequency, and also adjusted according to the variations of process and operating voltage and changes of the operating temperature as well.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供根据制造变化，工作电压变化和温度变化产生适当内部定时信号的半导体器件，以便在指定的等待时间和外部时钟频率下提供稳定的性能。解决方案：半导体器件具有：第一延迟电路块，其产生用于在由外部输入命令周期确定的列周期时间内工作的电路块的定时信号; 以及第二延迟电路块，其总延迟被调整为列周期时间与由外部时钟和等待时间确定的访问时间之间的差。关于延迟电路块，根据列延迟和工作频率适当地调整每个延迟电路的延迟，并且还根据工艺和工作电压的变化以及工作温度的变化进行调整。版权所有（C）2009，JPO＆INPIT

10. 发明专利

JP2008146934A Vacuum switchgear 有权
标题翻译：真空开关
公开(公告)号：JP2008146934A
公开(公告)日：2008-06-26
申请号：JP2006330920
申请日：2006-12-07
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMAZAKI MIKI , NAKAMURA MASAYUKI , KOBAYASHI MASAHITO , SUGAI DAISUKE
IPC分类号： H01H33/66
摘要： PROBLEM TO BE SOLVED: To suppress that a shaft of a bolt of a connecting part to connect an extraction conductor and a circuit conductor is fastened diagonally to the axis of a screw hole into which the bolt is screwed. SOLUTION: This has the screw hole 12 protruded and installed at an extraction conductor 6b, a bolt 9 which is screwed into the screw hole through a through hole 8b formed in the circuit conductor 8 corresponding to the screw hole 12 and which tighten the circuit conductor and the extraction conductor, and a pan spring 10 interposed and installed between the head of the bolt and the circuit conductor. The tip part 9a of a small diameter into which the bolt is screwed, a base part 9b of a large diameter into which the bolt is not screwed and a taper part 9c to link the tip part and the base part are formed. In the screw hole 12, the screw part 12a corresponding to the tip part of the bolt, a diameter-expanded part 12b which corresponds to the base part of the bolt and into which the bolt is not screwed, and a hole stepping part 12c which is formed corresponding to the taper part of the bolt are formed. The bolt is tightened by aligning the axial center of the screw hole at the taper part when the bolt is screwed into the screw hole. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了抑制连接引出导体和电路导体的连接部的螺栓的轴与螺栓拧入螺钉孔的轴线对角地固定。解决方案：螺钉孔12突出并安装在提取导体6b上，螺栓9通过形成在对应于螺钉孔12的电路导体8中的通孔8b拧入螺钉孔中，螺栓9被拧紧电路导体和提取导体，以及插入并安装在螺栓的头部和电路导体之间的盘簧10。形成螺栓拧入的小直径的前端部9a，螺栓未被螺纹拧入的大直径的基部9b和连结尖端部与基部的锥形部9c。在螺钉孔12中，与螺栓的前端部对应的螺纹部12a，与螺栓的基部对应的螺栓未螺合的直径扩大部12b，以及孔步进部12c 形成对应于螺栓的锥形部分。当螺栓拧入螺丝孔时，螺栓通过对准锥形部分处的螺钉孔的轴心被拧紧。版权所有（C）2008，JPO＆INPIT

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