专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2003058306A Portable apparatus 审中-公开
标题翻译：便携式设备
公开(公告)号：JP2003058306A
公开(公告)日：2003-02-28
申请号：JP2001250328
申请日：2001-08-21
申请人： Hitachi Ltd , Nec Corp , 日本電気株式会社 , 株式会社日立製作所
发明人： OKUMA YOSHIYUKI
IPC分类号： H03M11/08 , G06F3/023 , H04M1/02 , H04M1/247
摘要： PROBLEM TO BE SOLVED: To provide a portable apparatus including a portable telephone, a PDA (personal digital assistant), etc., capable of realizing reduction of key operations in Japanese input.
SOLUTION: In a portable telephone having 15 keys and cursors, parts of the 15 keys are set by dividing them into vowel parts and consonant parts, the vowel keys 10 are set to each of five keys '3, 6, 9, #, C' and the consonant keys 20 are set to each of nine keys '1, 4, 7, *, 2, 5, 8, 0, B'. In addition, punctuation keys 30 are allocated to a key 'A'. Thus, key operations are basically performed by 'vowel keys' + 'consonant keys' by dividing vowels and consonants, only twice of key depressions are required through the operations are conventionally required for five times in stages of 'o' and the input frequencies are reduced.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种能够实现日语输入中的键操作的减少的便携式电话，PDA（个人数字助理）等的便携式装置。解决方案：在具有15个键和光标的便携式电话中，15个键的部分通过将它们分成元音部分和辅音部分来设置，元音键10设置为五个键3,6,9，＃，C '和辅音键20被设置为9个键1,4,7，*，2，5，8，0，B'中的每一个。此外，将标点符号键30分配给键“A”。因此，按键操作基本上是通过划分元音和辅音进行“元音键”+“辅音键”，通过这些操作只需要两次按键，这些操作通常在'o'阶段需要五次，输入频率是减少

2. 发明专利

JP2007280606A Dram chips 有权
标题翻译： DRAM芯片
公开(公告)号：JP2007280606A
公开(公告)日：2007-10-25
申请号：JP2007183074
申请日：2007-07-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HORIGUCHI SHINJI , NAKAMURA MASAYUKI , OKUMA YOSHIYUKI , KAJITANI KAZUHIKO , NAKAGOME YOSHINOBU
IPC分类号： G11C11/4074 , G11C11/401
摘要： PROBLEM TO BE SOLVED: To especially reduce an active standby current by achieving low power consumption of a power supply circuit of a semiconductor memory. SOLUTION: A DRAM chip is provided with a first voltage supply means for supplying a first voltage to a plurality of sense amplifiers and a second voltage supply means for supplying a second voltage to a column decoder. The first voltage supply means includes a plurality of first voltage limiter circuits arranged in the number same as the number of plurality of memory banks correspondingly to each of the memory banks and a second voltage limiter circuit whose current supply capability is smaller than that of the first voltage limiter circuit. The second voltage supply means includes: a third voltage limiter circuit; a fourth voltage limiter circuit whose current supply capability is smaller than that of the third voltage limiter circuit and whose output node is connected to the output node of the third voltage limiter circuit; and a fifth voltage limiter circuit whose current supply capability is smaller than that of the third voltage limiter circuit and whose output node is connected to the output nodes of the third and fourth voltage limiter circuits. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过实现半导体存储器的电源电路的低功耗来特别地降低主动待机电流。解决方案：DRAM芯片设置有用于向多个读出放大器提供第一电压的第一电压供应装置和用于向列解码器提供第二电压的第二电压供应装置。第一电压供给装置包括多个与每个存储体相对应的多个存储体的数量相同的第一限压器电路;以及第二限压器电路，其电流供应能力小于第一限压电路。第二电压供给装置包括：第三限压器电路; 第四限压电路，其电流供给能力小于第三限压电路，其输出节点连接到第三限压电路的输出节点; 以及电流供给能力小于第三限压电路的第五限压电路，其输出节点连接到第三和第四限压器电路的输出节点。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2004259431A Dram 有权
公开(公告)号：JP2004259431A
公开(公告)日：2004-09-16
申请号：JP2004112616
申请日：2004-04-07
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HORIGUCHI SHINJI , NAKAMURA MASAYUKI , OKUMA YOSHIYUKI , KAJITANI KAZUHIKO , NAKAGOME YOSHINOBU
IPC分类号： G11C11/407 , G11C11/401
摘要： PROBLEM TO BE SOLVED: To reduce the electric power consumption of the power source circuit of a semiconductor memory, and more particularly, to reduce the standby current thereof. SOLUTION: A DRAM (dynamic RAM) is equipped with a plurality of memory banks which can be activated by respective activation commands and a plurality of power supply circuits which are disposed in corresponding to the respective memory banks, respectively receive external power supply voltages and output internal power supply voltages. The outputs of the power supply circuits are respectively connected to the corresponding memory banks and turn on the power source circuit component in correspondence to one of the memory banks among the power source circuits in response with the command for activating the memory bank and turn off the remaining power source circuits. COPYRIGHT: (C)2004,JPO&NCIPI

4. 发明专利

JP2004213895A Semiconductor device 有权
公开(公告)号：JP2004213895A
公开(公告)日：2004-07-29
申请号：JP2004112617
申请日：2004-04-07
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HORIGUCHI SHINJI , NAKAMURA MASAYUKI , OKUMA YOSHIYUKI , KAJITANI KAZUHIKO , NAKAGOME YOSHINOBU
IPC分类号： G11C11/401 , G11C11/407
摘要： PROBLEM TO BE SOLVED: To reduce power consumption of a power supply circuit of a semiconductor memory and to reduce an active standby current in particular.
SOLUTION: A plurality of memory banks that can be respectively and independently activated by an activation command and a plurality of power supply circuits provided respectively corresponding to the memory banks to respectively receive external power source voltage and output a prescribed internal power source voltage are provided. Outputs of the power supply circuits are respectively connected to corresponding memory banks, a power supply circuit provided in accordance with a corresponding bank among the power supply circuits are turned on in a response to a command for activating one of the memory banks, and the other power supply circuits are turned off.
COPYRIGHT: (C)2004,JPO&NCIPI

5. 发明专利

JP2003303928A Mounting package for semiconductor device 审中-公开
标题翻译：半导体器件安装封装
公开(公告)号：JP2003303928A
公开(公告)日：2003-10-24
申请号：JP2002107452
申请日：2002-04-10
申请人： Elpida Memory Inc , Hitachi Ltd , Renesas Eastern Japan Semiconductor Inc , エルピーダメモリ株式会社 , 株式会社ルネサス東日本セミコンダクタ , 株式会社日立製作所
发明人： MORI MORIHIKO , OKUMA YOSHIYUKI , TAKAHASHI YASUSHI , ONO TAKAO , SAKAGUCHI YOSHIHIRO , NAKAMURA ATSUSHI , MIYAZAWA TOSHIO
IPC分类号： H01L23/29 , H01L23/31 , H01L23/34 , H01L23/373
CPC分类号： H01L23/3135 , H01L23/3164 , H01L23/3737 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device mounting package, in which heat- dissipating characteristics of an LSI are improved.
SOLUTION: A package 10 is for mounting a semiconductor device (LSI) 15 that has an surface exposed to an atmosphere, and the exposed surface is coated with a coating material 16, such as a tape or a seal, etc.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种其中提高了LSI的散热特性的半导体器件安装封装。解决方案：封装10用于安装具有暴露于大气的表面的半导体器件（LSI）15，并且暴露的表面涂覆有例如带或密封件等的涂层材料16。 P>版权所有（C）2004，JPO

6. 发明专利

JPH04310691A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH04310691A
公开(公告)日：1992-11-02
申请号：JP10318491
申请日：1991-04-08
申请人： HITACHI LTD
发明人： MATSUYOSHI SATOSHI , YANAGISAWA KAZUMASA , OGUCHI SATOSHI , OKUMA YOSHIYUKI , HIRAISHI ATSUSHI , AOKI HIDEYUKI , MIURA YASUHIRO
IPC分类号： G11C11/41 , G11C11/401 , G11C11/409 , H01L27/10
摘要： PURPOSE:To curtail the power consumption which follows an equalization processing and to reduce the load to an equalization control signal EQA while optimizing an execution timing of the equalization processing of common data lines CD0-CD7 by equalizing circuit UEQ0-UEQ7 at every block MB0, etc., and as a result, 1 to promote the tendency of its low power consumption and high speed while stabilizing an operation of a Bi.CMOS static type RAM, etc., provided with plural memory blocks containing the equalizing circuit. CONSTITUTION:The equalization processing of a common data line by equalizing circuits UEQ0-UEQ7 is set selectively to an operating state in accordance with an equalization control signal EQA being common to block selecting signals USO and BS0-BS3 for activating selectively the corresponding memory block MB0, etc. Also, this device is provided with an equalization control circuit EQC for setting selectively the corresponding equalizing circuits UEQ0-UEQ7 to an operating state at every memory block MB0, etc., and also, adjusting an execution timing of the equalization processing.

7. 发明专利

JPH04295880A ELECTRONIC APPLIANCE 失效
公开(公告)号：JPH04295880A
公开(公告)日：1992-10-20
申请号：JP6149191
申请日：1991-03-26
申请人： HITACHI LTD
发明人： OKUMA YOSHIYUKI
IPC分类号： G03B21/10 , G06F1/16 , G09F9/00
摘要： PURPOSE:To offer the display technique by which a personal computer and a word processor can be reduced in weight and miniaturized. CONSTITUTION:As a display device of a personal computer and a word processor, a projector 2 is used instead of using a CRT or a liquid crystal panel, and as for the display surface, a panel 4 provided integrally with a main body 1 or the wall surface in a room is utilized. Since the projector which can be miniaturized, comparing with the CRT or the liquid crystal panel is used as a display device, the whole of the personal computer and the word processor can be miniaturized and reduced in weight by its difference.

8. 发明专利

JPH04271099A STATIC RAM 失效
公开(公告)号：JPH04271099A
公开(公告)日：1992-09-28
申请号：JP5334491
申请日：1991-02-25
申请人： HITACHI LTD
发明人： YANAGISAWA KAZUMASA , HIRAISHI ATSUSHI , AOKI HIDEYUKI , OGUCHI SATOSHI , OKUMA YOSHIYUKI
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04 , H01L21/82 , H01L27/10
摘要： PURPOSE:To increase the storage capacity with simple constitution by carrying out a column selecting operation with complementary data lines composed of 8 pairs as a unit. CONSTITUTION:A unit column decoder circuit UDCR is provided on pitches corresponding to the 8 pairs of the complementary data lines CDL 0 to CDL 7, the column selecting operation is carried out with the complementary data lines composed of 8 pairs as the unit and a space in a horizontal direction for the corresponding decoder circuit is taken as wide as that for the 8 pairs of the complementary data lines. Thus, a decoding circuit UDCR with a circuit of a relatively big size constituted of a fusing means F, a selective signal YS of the column selecting circuit including MOSFETQ 9 and inverter circuits N3 and N4 by which a control signal INH is formed by detecting the presence of the its cutting, gate circuits G1 to G4 by which the control signal PL of a negative MOSFET is formed and inverter circuits N5 and N6 is formed.

9. 发明专利

JPH02116159A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02116159A
公开(公告)日：1990-04-27
申请号：JP26802888
申请日：1988-10-26
申请人： HITACHI LTD
发明人： OKUMA YOSHIYUKI
IPC分类号： H01L27/10 , H01L27/108
摘要： PURPOSE:To improve the degree of integration of a wafer scale memory by forming in separately a memory cell section and peripheral circuit section in each wafer chip area, and making an address space of the peripheral circuit section larger than the capacity of the memory cell section. CONSTITUTION:Many chip areas 2 are disposed on the principal surface of a wafer 1 in the form of a lattice. In each area 2 six memory cell sections 3 and one peripheral circuit section 4 are formed in separation. In the chip area 2 there are electrically connected the memory cell 3, the circuit section 4, and the area 2 with each other, and the whole of the wafer 1 forms one memory circuit system. The memory cell section 3 comprises a MOS type DRAM for example and the peripheral circuit section 4 includes an address space several times the memory cell section 3. The one peripheral circuit section 4 can drive the maximum four memory cell sections 3.

10. 发明专利

JPH1127132A IMPEDANCE MATCHING CIRCUIT AND SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH1127132A
公开(公告)日：1999-01-29
申请号：JP17607597
申请日：1997-07-01
申请人： HITACHI LTD
发明人： OKUMA YOSHIYUKI
IPC分类号： G11C11/417 , G11C11/401 , G11C11/409 , H03K19/0175
摘要： PROBLEM TO BE SOLVED: To match an output impedance of an output buffer with an impedance of a transmission line automatically by allowing a counter to count up when an output level of the output buffer does not exceed a reference voltage and allowing the counter to count down when the output level exceeds the reference voltage and using the count to select an output impedance adjustment element of the output buffer. SOLUTION: A 1st comparator circuit CMP1 compares a voltage level Vno of an output node No of an output buffer OPB with a reference voltage Vref1. A 2nd comparator circuit CMP2 compares the voltage Vno with a reference voltage Vref2, and counters CNT1, CNT2 count up or down depending on the comparison result by the comparator circuits CMP1, CMP2. Then a signal of each bit of the counters CNT1, CNT2 is fed to gates of impedance adjustment MOSFETs Qp1-Qpn, Qn1-Qnn.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式