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1. 发明专利

JP2004096119A Semiconductor device and its manufacturing method 审中-公开
公开(公告)号：JP2004096119A
公开(公告)日：2004-03-25
申请号：JP2003320604
申请日：2003-09-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HOSHINO YUTAKA , IKEDA SHUJI , YOSHIDA ISAO , KANBARA SHIRO , KAWAKAMI MEGUMI , MIYAKE TOMOYUKI , MORIKAWA MASATOSHI
IPC分类号： H01L29/41 , H01L21/768 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088 , H01L29/417 , H01L29/78
CPC分类号： H01L29/41758 , H01L29/4175 , H01L29/7835 , H01L2224/49175 , H01L2924/13091 , H01L2924/19105 , H01L2924/3011 , H01L2924/30111 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To make fine a MOSFET for high frequency amplification having a drain offsetting region and, at the same time, lower its on-resistance. SOLUTION: In the MOSFET, electrode leading-out conductor plugs 13(p1) are respectively provided on a source region 10, a drain region 9, and a reach-through layer 3(4). Two layers of first-layer wiring 11s and 11d(M1) are respectively connected to the plugs 13(p1), and two layers of second-layer wiring 12s and 12d for back lining are respectively connected to the first-layer wiring 11s and 11d(M1) on the plugs 13(p1). COPYRIGHT: (C)2004,JPO

2. 发明专利

JP2004096118A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2004096118A
公开(公告)日：2004-03-25
申请号：JP2003320603
申请日：2003-09-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HOSHINO YUTAKA , IKEDA SHUJI , YOSHIDA ISAO , KANBARA SHIRO , KAWAKAMI MEGUMI , MIYAKE TOMOYUKI , MORIKAWA MASATOSHI
IPC分类号： H01L21/768 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088 , H01L29/417 , H01L29/78
CPC分类号： H01L29/7835 , H01L29/4175 , H01L29/41758 , H01L2224/48227 , H01L2224/49111 , H01L2224/49175 , H01L2924/13091 , H01L2924/19105 , H01L2924/3011 , H01L2924/30111 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To make fine a MOSFET for high frequency amplification having a drain offsetting region fine and, at the same time, lower its on-resistance. SOLUTION: In the MOSFET, electrode leading-out conductor plugs 13(p1) are respectively provided on a source region 10, a drain region 9, and a reach-through layer 3 (4). Two layers of first-layer wiring 11s and 11d(M1) are respectively connected to the conductor plugs 13(p1), and two layers of second-layer wiring 12s and 12d for back lining are respectively connected to the first-layer wiring 11s and 11d(M1) on the plugs 13(p1). COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了使具有漏极偏移区域的高频放大的MOSFET精细化，并且同时降低其导通电阻。解决方案：在MOSFET中，电极引出导体插头13（p1）分别设置在源极区域10，漏极区域9和贯通层3（4）上。两层第一层布线11s和11d（M1）分别连接到导体插头13（p1），两层用于背衬的第二层布线12s和12d分别连接到第一层布线11s和 11d（M1）在插头13（p1）上。版权所有（C）2004，JPO

3. 发明专利

JP2003309264A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2003309264A
公开(公告)日：2003-10-31
申请号：JP2003093135
申请日：2003-03-31
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAKAMOTO MITSUZO , YOSHIDA ISAO , MORIKAWA MASATOSHI , OTAKA SHIGEO
IPC分类号： H01L27/06 , H01L21/76 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/08 , H01L27/088 , H01L29/78 , H01L29/786 , H02H7/20 , H03K17/08
CPC分类号： H01L29/7803 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/49113 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a power MOSFET excellent in mounting efficiency which includes overheat protecting structure or overcurrent-protecting structure. SOLUTION: In the semiconductor device wherein a first semiconductor chip and a second semiconductor chip are mounted on the same package by plastic molding, the power MOSFET is formed in the first semiconductor chip, and the second semiconductor chip forms a circuit for protecting the power MOSFET. As a result, the power MOSFET which includes a miniaturized protecting circuit in the same package can be obtained. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供具有优异的安装效率的功率MOSFET，其包括过热保护结构或过电流保护结构。解决方案：在通过塑料模制将第一半导体芯片和第二半导体芯片安装在相同封装上的半导体器件中，功率MOSFET形成在第一半导体芯片中，并且第二半导体芯片形成用于保护的电路功率MOSFET。结果，可以获得包括相同封装中的小型化保护电路的功率MOSFET。版权所有（C）2004，JPO

4. 发明专利

JP2002343960A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002343960A
公开(公告)日：2002-11-29
申请号：JP2001141284
申请日：2001-05-11
申请人： HITACHI LTD
发明人： SHINTO MIO , MORIKAWA MASATOSHI , YOSHIDA ISAO , FUJIOKA TORU , KUROTANI KINGO
IPC分类号： H01L23/52 , H01L21/265 , H01L21/3205 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device wherein the reduction of on- resistance and restraint of characteristic deterioration which is caused by hot carriers are realized. SOLUTION: A shield conducting film 10 which is electrically connected with a source electrode 12 is arranged between a gate electrode 3 and a drain electrode 13 of an FET. In a drain offset layer 8, two kinds of n-type semiconductors are subjected to double ion implantation, and the layer 8 has a double layer structure constituted of an n-type semiconductor region 8bb in which ions are implanted shallowly and an n-type semiconductor region 8aa in which ions are implanted deeply. The n-type semiconductor region 8bb of the drain offset layer in a gate electrode end, wherein ions are implanted shallowly, is formed being shifted to the drain side, and an LDD wherein the concentration of impurity is low is arranged on a gate end side of the drain offset layer. As a result, the on-resistance is reduced and output power can be improved while the reliability of a high frequency power MOSFET is ensured.

5. 发明专利

JP2001094094A SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 失效
公开(公告)号：JP2001094094A
公开(公告)日：2001-04-06
申请号：JP26666899
申请日：1999-09-21
申请人： HITACHI LTD
发明人： HOSHINO YUTAKA , IKEDA SHUJI , YOSHIDA ISAO , KANBARA SHIRO , KAWAKAMI MEGUMI , MIYAKE TOMOYUKI , MORIKAWA MASATOSHI
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8234 , H01L23/482 , H01L23/532 , H01L27/04 , H01L27/088 , H01L29/417
摘要： PROBLEM TO BE SOLVED: To realize fine patterning and reduction of ON resistance in an MOSFET for high frequency amplification having a drain offset region. SOLUTION: Conductor plugs 13(P1) for leading out electrode are provided on a source region 10, a drain region 9 and a reach through layer 3(4). The conductor plugs 13(P1) are connected, respectively, with first layer interconnections 11s, 11d(M1) which are connected, on the conductor plugs 13(P1), with second layer interconnections 12s, 12d for lining.

6. 发明专利

JPH05129597A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH05129597A
公开(公告)日：1993-05-25
申请号：JP29124591
申请日：1991-11-07
申请人： HITACHI LTD
发明人： SAKAMOTO MITSUZO , YOSHIDA ISAO , MORIKAWA MASATOSHI
IPC分类号： H01L21/336 , H01L29/78
摘要： PURPOSE:To provide an LSI having a shielding structure of a power LDMOS transistor with a sense FET. CONSTITUTION:A first conductivity type high concentration second semiconductor region 2 is provided on a first conductivity type first semiconductor region 1, and a second conductivity type fourth semiconductor region 3a isolated by a first conductivity type semiconductor region 4 so annularly formed as to reach the region 2 from the main surface of a semiconductor is used as a drain of the transistor. A plurality of first conductivity type fifth semiconductor regions 7b, 7c are formed in the region 3a, and at least one of them is used as a body of a mirror MOS transistor of a sense FET. Thus, an LDMOS shielding structure LSI can be realized without reducing the resistance of the sense FET.

7. 发明专利

JPH03109775A INSULATION-GATE-TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03109775A
公开(公告)日：1991-05-09
申请号：JP24627889
申请日：1989-09-25
申请人： HITACHI LTD
发明人： SAKAMOTO MITSUZO , KURE TOKUO , OKABE TAKEAKI , YOSHIDA ISAO , MORIKAWA MASATOSHI
IPC分类号： H01L29/78
摘要： PURPOSE:To reduce ON resistance and improve strength against damage by burying a gate electrode in silicon and forming not only a source and a body but also a source electrode self-alignedly with a gate pattern. CONSTITUTION:A gate electrode 8 is buried in a groove formed on a principal face of a semiconductor matrix, and a source region and a body region are formed self-alignedly with this gate electrode 8. Further a source electrode 15 for connecting the source with the body is buried on the principal face of the semiconductor matrix self-alignedly with the gate electrode 8. In this case a channel of a MIS transistor can be formed in a longitudinal direction while the gate can be formed self-alignedly not only with the source and the body but also with the source electrode which connects the body with the source. Thus strength against damage, ON resistance and switching characteristics can be improved.

8. 发明专利

JPH03105979A INSULATED-GATE SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH03105979A
公开(公告)日：1991-05-02
申请号：JP24200789
申请日：1989-09-20
申请人： HITACHI LTD
发明人： YOSHIDA ISAO , OTAKA SHIGEO , IIJIMA TETSUO , FUJITA YUZURU , MORIKAWA MASATOSHI , SHIMIZU SHUICHI , KOBAYASHI MASAYOSHI , KURE TOKUO
IPC分类号： H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/78
摘要： PURPOSE:To make a MOSFET cell fine, to increase a mounting density, to make an ON resistance low and to increase a breakdown-strength by a method wherein a size of a source region is prescribed in a self-aligned manner by an insulating film at a sidewall part of a gate electrode and a U-groove contact which is shallower than a depth of the source region is formed. CONSTITUTION:A source region of a power MOSFET is composed of a shallow low-concentration region 11 and a deep high-concentration region 12. A length in a transverse direction of the source region is self-aligned by a U-groove part to be used as a source electrode 9 and its size is uniform. Consequently, a size of a base region connected to the source electrode 9 is secured to be definite. As a result, a base resistance can be suppressed to be small, and a parasitic bipolar transistor operation is not caused.

9. 发明专利

JPH01235369A INTEGRATED-CIRCUIT SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01235369A
公开(公告)日：1989-09-20
申请号：JP6038388
申请日：1988-03-16
申请人： HITACHI LTD
发明人： MORIKAWA MASATOSHI , YOSHIDA ISAO , KAWAMOTO YOSHIFUMI , KOJIMA KOJI , OKABE TAKEAKI
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/08 , H01L27/088 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To make a microminiaturized MOSFET and a transistor of high breakdown strength and for power coexist by making an LDD structure MOSFET and a lateral type power MOSFET coexist and simultaneously forming a low impurity concentration layer for LDD structure and an offset layer for the power MOSFET under the same conditions of formation. CONSTITUTION:The surface of a P-type substrate 3 is oxidized, then a P-type well layer 4 is shaped through well-photoetching, the implantation of B ions and drive-in, and LOCOS isolation is preformed through the deposition of Si3N4, L-photoetching and thermal oxidation. A gate oxide film 9 is formed, the deposition of polycrystalline Si, phosphorus treatment and the photoetching of a gate electrode are performed, and P ions are implanted 17. A side-wall 10 for the gate electrode 9 is shaped through the deposition of a high-temperature low-pressure oxide film and anisotropic etching, P ions are implanted 19 through a photoetching process 18, and a high-concentration N-type layer 5 is formed. A high-concentration P-type layer 6 is shaped, and an insulating film 12 is deposited. The boring of a contact hole, the wiring of an Al first layer 13, the deposition of an inter-layer insulating film 14, the boring of a through-hole, the wiring of an Al fist layer 15 and the formation of a protective film 16 are successively executed. Accordingly, an LDD structure MOSFET and a lateral type power MOSFET can be made to coexist through a simple process.

10. 发明专利

JP2001168647A HIGH FREQUENCY POWER AMPLIFICATION MODULE AND RADIO COMMUNICATION EQUIPMENT 失效
公开(公告)号：JP2001168647A
公开(公告)日：2001-06-22
申请号：JP35335599
申请日：1999-12-13
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： NUMANAMI MASAHITO , AKAMINE HITOSHI , SHIBUYA TAKESHI , ADACHI TETSUAKI , MORIKAWA MASATOSHI , NUNOKAWA YASUHIRO
IPC分类号： H03F3/189 , H01L29/10 , H01L29/417 , H01L29/78 , H01Q11/12 , H03F1/02 , H03F1/22 , H03F1/32 , H03F3/60 , H03F3/72 , H03G1/00 , H04B1/04 , H04K1/02
摘要： PROBLEM TO BE SOLVED: To provide a high frequency power amplification module and radio communication equipment which enable a GSM system (nonlinear operation) and an EDGE system (linear operation) to coexist in the same circuit. SOLUTION: This high frequency power amplification module is of a multistage amplification configuration. External terminals are defined as an input terminal, an output terminal, a control terminal, a 1st reference potential Vdd, a 2nd reference potential Vss (ground) and a mode switching terminal, a 1st stage semiconductor amplifying element is composed of a dual gate FET, a signal from the control terminal is applied to a 1st gate G1 being close to the drain through a resistance, a high frequency signal supplied from the input terminal is applied to a 2nd gate G2 and a potential obtained by applying voltage division to a signal voltage from the control circuit in a bias circuit is also applied to the gate G2, and a transistor for mode switching is turned ON/OFF by a signal from the mode switching terminal. When the transistor is ON, an amplification system for a GSM (nonlinear operation: maximum output is 36 dBm) is made active, and when the transistor is OFF, an amplification system for an EDGE (linear operation: maximum output is 29 dBm) is made active.

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