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1. 发明专利

JP2005166856A Apparatus and method for semiconductor device testing and semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件测试和半导体器件制造方法的装置和方法
公开(公告)号：JP2005166856A
公开(公告)日：2005-06-23
申请号：JP2003402422
申请日：2003-12-02
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MATSUO MITSUHISA , MATSUNAGA TOSHIHIRO , TANAKA TAMOTSU
IPC分类号： H01L23/12 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a method for testing a semiconductor device for strength against impact, wherein quantification is easy and loss due to friction drag or the like is low.
SOLUTION: The semiconductor device testing apparatus wherein an impact is applied to a part of a specimen semiconductor device for testing the part for strength, comprises a stage for fixing immovable the specimen in the vertical direction as the direction of impact application, a piston movable in the direction of impact application with one of its ends in contact with the part of the specimen to be tested, and a plummet that freely falls in the direction of impact application for colliding with the other end of the piston. By using this method, friction drag is reduced because impact is applied to the specimen by a freely falling plummet, and because the impact of the plummet is applied to the specimen through a piston one of whose end is in contact with the specimen.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于测试抗冲击强度的半导体器件的方法，其中量化容易并且由于摩擦阻力等而导致的损耗低。解决方案：将冲击施加到用于强度测试的部件的试样半导体器件的一部分的半导体器件测试装置包括用于沿垂直方向固定试样的冲击应用方向的台，活塞可沿着冲击施加的方向移动，其一端与被测试样品的一部分接触，以及一个自动落在冲击施加方向上以与活塞另一端碰撞的倾斜器。通过使用这种方法，由于通过自由下落的对接头对样品施加冲击，并且由于通过其端部与试样接触的活塞将试样施加到试样上，因此摩擦阻力减小。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2004260051A Semiconductor device manufacturing method, and semiconductor device 审中-公开
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：JP2004260051A
公开(公告)日：2004-09-16
申请号：JP2003050642
申请日：2003-02-27
申请人： Hitachi Ltd , Renesas Eastern Japan Semiconductor Inc , 株式会社ルネサス東日本セミコンダクタ , 株式会社日立製作所
发明人： SHIRAISHI TOMOHIRO , TANAKA TAMOTSU , NAGATA TATSUYA , NAKAMARU TSUTOMU , ARAI HIROSHI
IPC分类号： H01L23/12 , H01L23/34 , H01L23/36
CPC分类号： H01L2224/48091 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method and a semiconductor device having a BGA package configuration with a high heat radiating characteristic.
SOLUTION: The semiconductor device manufacturing method has a process for mounting a semiconductor chip 3 on a wiring board 2 via a die bonding material 4, a process for connecting then electrically the semiconductor chip 3 and the wiring board 2 via bonding wires 5, a process for forming then on the wiring board 2 a sealing resin 6 for covering therewith the semiconductor chip 3 and the bonding wires 5, a process for forming thereafter solder balls 9 on the rear surface of the wiring board 2, and a process for adhering a heat radiating plate 8 to the top surface of the sealing resin 6 via an adhering material 7. In this case, an organic material film 8a having high emissivity is applied to the opposite side surface of the heat radiating plate 8 to its surface side whereon it is adhered to the sealing resin 6.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：提供具有高散热特性的具有BGA封装结构的半导体器件制造方法和半导体器件。解决方案：半导体器件制造方法具有通过管芯接合材料4将半导体芯片3安装在布线板2上的工艺，通过接合线5将半导体芯片3和布线板2电连接的工艺在该布线基板2上形成用于覆盖半导体芯片3和接合线5的密封树脂6，在该布线基板2的背面形成后述的焊锡球9的工序的工序，通过粘接材料7将热辐射板8粘合到密封树脂6的顶面。在这种情况下，将具有高发射率的有机材料膜8a施加到散热板8的相对侧表面在那里粘附到密封树脂6上。（C）2004，JPO＆NCIPI

3. 发明专利

JPH0745662A ADHERING STRUCTURE FOR METAL MASK 失效
公开(公告)号：JPH0745662A
公开(公告)日：1995-02-14
申请号：JP18947393
申请日：1993-07-30
申请人： HITACHI LTD
发明人： UDA TAKAYUKI , TANAKA TAMOTSU
IPC分类号： C23C14/04 , H01L21/321 , H01L21/60 , H05K3/14
摘要： PURPOSE:To reduce the thickness of a metal mask and, at the same time, to improve the adhesive property of the mask by closely sticking the mask to a substrate by means of a magnetizing member provided on the rear surface of the substrate. CONSTITUTION:When the switch of an electromagnet 3 is turned on after aligning a metal mask 2, the mask 2 is closely stuck to a semiconductor wafer 1. The wafer 1, mask 2, and electromagnet 3 fixed on a fixing member 4 are put in a BLM film forming device and CCB bumps are formed on the wafer 1. Since the mask 2 is formed of such a ferromagnetic material as the 42-alloy, the mask is closely stuck to the substrate 1 by utilizing the magnetic force of the electromagnet 3. Therefore, the mask 2 does not bloat, but closely adhere to the wafer 1. In addition, since the mask 2 can be formed in a desired thickness, the surface of the formed CCB bumps can be flattened and electrical inspections can be smoothly performed with probes.

4. 发明专利

JPH06169026A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06169026A
公开(公告)日：1994-06-14
申请号：JP31974292
申请日：1992-11-30
申请人： HITACHI LTD
发明人： YAMADA TAKEO , KOBAYASHI TORU , ISOMURA SATORU , SHIMIZU ATSUSHI , ITO YUKO , HAYASHIDA TETSUYA , SATO TOSHIHIKO , TANAKA TAMOTSU
IPC分类号： H01L23/02 , H01L23/04 , H01L23/08 , H01L23/24 , H01L23/50
摘要： PURPOSE:To provide a chip carrier type semiconductor integrated circuit device which enhances connection reliability between a semiconductor chip and a package board. CONSTITUTION:A cap 6 which seals a semiconductor chip 5 is made of metal or synthetic resin and designed to absorb a tensile stress which applies to a soldering bump 4 produced by differential thermal expansion coefficients of the semiconductor chip 5, a package board 2 and the cap 6 by deforming the shape of the cap 6.

5. 发明专利

JPH03173294A ELECTRONIC EQUIPMENT 失效
公开(公告)号：JPH03173294A
公开(公告)日：1991-07-26
申请号：JP31063989
申请日：1989-12-01
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TATE HIROSHI , TANAKA TAMOTSU
IPC分类号： H04N5/00 , H04Q9/00
摘要： PURPOSE:To prevent a careless operation from a remote location by using a remote control unit so as to disable the function of an electronic device from the device main body. CONSTITUTION:When a 3rd party is going to touch an operation panel of a device main body 2 during a prescribed operation of an electronic device 1a, an operation lock button in a remote control unit 3 is depressed to send an optical signal disabling the operation of the function from the device main body 2. A reception section 4 detects and decodes the optical signal to send an operation state control section 5 and a control signal to disable the operation from the device main body 2 is sent to a mechanical setting means 7a to move the operation panel inward thereby forming the shield state.

6. 发明专利

JPH02156539A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02156539A
公开(公告)日：1990-06-15
申请号：JP31091588
申请日：1988-12-08
申请人： HITACHI LTD
发明人： TANAKA TAMOTSU , MIYAMOTO HIROAKI , HAYASHIDA TETSUYA , YOSHIDA IKUO
IPC分类号： H01L21/60 , H01L21/321
摘要： PURPOSE:To enable metal projection electrodes to be formed in a large size by depositing a photosensitive resist material on the surface of a semiconductor substrate to provide a first peeling layer, forming a first opening in a region of the first peeling layer where an electrode to be formed, attaching a second peeling layer and forming a second opening smaller than the first opening over the first opening. CONSTITUTION:Liquid-type negative resist film 51 is applied on a surface protecting film 41 having an underlying electrode 50 for solder projection electrodes formed thereon. Then, a mask patterned as required is put on the resist film and the resist is irradiated with ultraviolet rays through the mask so as to expose the resist other than the regions thereof where metal projection electrodes are to be formed. The exposed resist is then removed by developing and an opening 51a is formed at a position as required over the electrode 50. A film-type methacryl negative resist film 52 is attached onto the liquid-type negative resist film 51 and an opening 52a having a diameter smaller than that of the opening 51a is formed over the opening 51a in a similar manner. According to this method, the size of ar opening 55 can be determined correctly and the solder projection electrodes can be formed in a large size.

7. 发明专利

JPH01194439A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01194439A
公开(公告)日：1989-08-04
申请号：JP1980488
申请日：1988-01-29
申请人： HITACHI LTD
发明人： UDA TAKAYUKI , TANAKA TAMOTSU , EMOTO YOSHIAKI , KURODA SHIGEO
IPC分类号： H01L21/28 , B23K1/00 , H01L21/306 , H01L21/3205 , H01L21/321 , H01L21/60
摘要： PURPOSE:To improve the exfoliation of a region not formed with a conductor film of a second resist film by forming an opening formed with a dummy conductor film on a region not formed with the conductor film in a first resist film disposed on a substrate and a second resist film formed on a conductor film forming region, and invading an exfoliation solution on the second film through the opening. CONSTITUTION:A first resist film 18 is formed on a passivation film 4I of a region not formed with a salient-electrode (conductor film) 8 of a mother chip 4. Then, a second resist film 19 is formed on a whole substrate including the film 4I and the film 18. Thereafter, a first opening 20A is formed at a part formed with the electrode 8 of the film 19 (on an inner terminal P1), and a second opening 20B for forming a dummy salient-electrode 8A is formed on a region not formed with the electrode 8. The electrode 8 is formed on a barrier metal layer 4K on wirings 4G of the inner terminal P1 in the opening 20A of the film 19. An exfoliation solution is impregnated to the film 19 through the opening 20B. Then, the films 19, 18 are removed. Since the film 18 can be removed in the step of removing the film 19, manufacturing steps can be shortened.

8. 发明专利

JPH06188284A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06188284A
公开(公告)日：1994-07-08
申请号：JP33847992
申请日：1992-12-18
申请人： HITACHI LTD
发明人： HIROKAWA JUN , TANAKA TAMOTSU , YOSHIDA IKUO , UDA TAKAYUKI , SATO TOSHIHIKO , HAYASHIDA TETSUYA , ISHIDA TAKASHI
IPC分类号： H01L21/60 , H01L21/321
摘要： PURPOSE:To improve connection reliability on the interface between CCB solder and an intermetallic compound formed on BLM by using Ni for the BLM in a CCB connection. CONSTITUTION:This is a semiconductor integrated circuit being provided with the structure face-down bonding a semiconductor chip through a CCB solder bump where an aluminum conductor wiring (inner wiring) 12 is formed through an insulating film 11 consisting of SiO2. Further, this is a semiconductor integrated circuit device to be composed of a semiconductor chip 10 where a surface protective insulating layer (electric insulating layer) 13 is formed, BLM 17 coming in contact with the aluminum conductor wiring (inner wiring) 12, and consisting of a CR layer 14, an Ni-28 atomic % Cu alloy layer 15 and an Au layer 16, and CCB solder 1A consisting of Pb 18 and Sn 19 while connecting to BLM 17.

9. 发明专利

JPH0290624A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0290624A
公开(公告)日：1990-03-30
申请号：JP24357788
申请日：1988-09-28
申请人： HITACHI LTD
发明人： YOSHIDA IKUO , TANAKA TAMOTSU , MIYAMOTO HIROAKI , HAYASHIDA TETSUYA
IPC分类号： H01L21/60 , H01L21/321
摘要： PURPOSE:To sharply reduce working hours and to prevent the remaining of a foreign substance by a method wherein, after the bonding force between an exfoliation layer and an insulating film has been attenuated, the desired pattern is left on the surface of an insulator by mechanically peeling off the exfoliation layer and a coating layer. CONSTITUTION:After an exfoliation layer 53, consisting of a resist material, has been deposited on the region other than the BLM electrode forming region of a surface protective film 41, a solder layer, which is a coating layer 56, is deposited on the exfoliation layer 53, and also a bump metal layer 57 is deposited on the region having no exfoliation layer in such a manner that they are separated from each other. After the bonding force between the exfoliation layer 53 and the surface protective film 41 has been attenuated by irradiation with ultraviolet rays, the exfoliation layer 53 and the coating layer 56 are mechanically exfoliated from the surface protective film 41, and the solder layer which constitutes a bump electrode 4 is made to survive.

10. 发明专利

JPH01286448A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01286448A
公开(公告)日：1989-11-17
申请号：JP11465188
申请日：1988-05-13
申请人： HITACHI LTD
发明人： TANAKA TAMOTSU , EMOTO YOSHIAKI , SATO TOSHIHIKO , KURODA SHIGEO , UDA TAKAYUKI
IPC分类号： H01L23/52 , H01L21/314 , H01L21/3205 , H01L21/60 , H01L23/556
摘要： PURPOSE:To effectively prevent the generation of soft error without decreasing the throughput of solder bump forming process by leaving a part of a metal film for solder substratum electrode stuck on a passivation film of a semiconductor wafer, above an integrated circuit forming region. CONSTITUTION:By using sputtering method or the like, thin films of, e.g., chromium (Cr), copper (Cu) and gold (Au) are stuck in order on the surface of a wafer 1; these thin films are etched by using a resist mask; a solder substratum electrode 5 is formed on the surface of an Al electrode pad 4; an alpha-ray shielding layer 6 is formed above an integrated circuit forming region. After a solder film composed of tin(Sn)-lead(Pb) alloy is selectively stuck on the surface of the solder substratum electrode 5, said solder film is subjected to wet-back in a reflow furnace, thereby forming a hemispherical solder bump 7.

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