专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH1063693A SIGNAL DELAY TIME CALCULATING METHOD FOR LOGIC CIRCUIT AND DISPLAY METHOD FOR DELAY TIME 失效
公开(公告)号：JPH1063693A
公开(公告)日：1998-03-06
申请号：JP21828096
申请日：1996-08-20
申请人： HITACHI LTD
发明人： KATO NAOKI , MIKI YOSHIO , HIYAMA TORU , KONO ICHIRO
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To enable the high-speed and high-accuracy calculation of delay time even in a large scale logic circuit by calculating high-accuracy delay time by performing circuit simulation, and updating the signal delay time between paths stored as the result of static delay calculation processing with this delay time. SOLUTION: In circuit simulation processing 106, the analyzed result 118 is prepared by executing circuit simulation to circuit simulation data 117 prepared from circuit simulation data generating processing 104 and circuit simulation input signal generating processing 105. In delay time calculating processing 107, the delay time of the path is calculated from this analyzed result and stored in a high-accuracy path delay information file 119. In delay time correcting processing 108, the signal delay time of the path delay information file 112 stored as the calculated result of static delay calculating processing 101 is updated with the delay time in the high-accuracy path delay information file 119.

2. 发明专利

JPH07282099A METHOD FOR INPUTTING WIRING PATTERN 失效
公开(公告)号：JPH07282099A
公开(公告)日：1995-10-27
申请号：JP7182994
申请日：1994-04-11
申请人： HITACHI LTD , HITACHI SOFTWARE ENG
发明人： TANIGUCHI TOMIO , SUZUKI KATSUKI , SHIBUYA HIROKO , HIYAMA TORU
IPC分类号： G06F17/50 , H05K3/00
摘要： PURPOSE:To facilitate the input of wiring patterns by inputting wiring patterns by each signal, thereby, correcting terminal, through-hole, and existing wiring pattern automatically deciding the name of a wiring pattern layer, automatically setting the through-hole at a branching point, and bypassing an obstacle, such as an area prohibiting a wiring pattern, etc. CONSTITUTION:After selecting the name of a signal for wiring input, information of the signal, adjacent other wiring pattern information and information on the obstacle such as the area prohibiting the wiring pattern, etc., are generated and with respect to a coordinate specified by a mouse, correction to a connection object (204), the decision of the name of the wiring pattern layer (207) and the decision of the through-hole (209) are executed. When an obstacle exists on the wiring pattern to set, the wiring pattern is corrected to be a shape which bypasses the obstacle (212, 213) and after then, the wiring pattern is displayed. Then, by inputting the wiring patterns by each signal name so as to correct to the connection object, to automatically decide the wiring layer of the wiring pattern and the through-hole and to bypass an obstacle, etc., the input of the wiring patterns can be facilitated.

3. 发明专利

JPH0275031A PROGRAM FOR ELECTRONIC COMPUTER 失效
公开(公告)号：JPH0275031A
公开(公告)日：1990-03-14
申请号：JP22661988
申请日：1988-09-12
申请人： HITACHI LTD
发明人： HIYAMA TORU , SAKATAYA YOSHINORI
IPC分类号： G06F11/28 , G06F1/24 , G06F9/445 , G06F9/45 , G06F12/00
摘要： PURPOSE:To detect the defects with high efficiency during the execution of a test for program having the defective initialization by using a function that can perform the initialization with an optional binary pattern designated by a programmer. CONSTITUTION:A function is added to a linkage editor/loader to perform the initialization of a memory based on an optional binary pattern which is externally designated. This function is used by a programmer as necessary. Thus a defect is easily detected when a program to be linked has an initialization defect and the value of the program is not coincident with the designated binary pattern. Then the defect is easily analyzed with high reproducibility.

4. 发明专利

JPH01166262A WIRING SYSTEM 失效
公开(公告)号：JPH01166262A
公开(公告)日：1989-06-30
申请号：JP32393987
申请日：1987-12-23
申请人： HITACHI LTD
发明人： HIYAMA TORU
IPC分类号： H05K3/00 , G06F17/50
摘要： PURPOSE:To automatically realize parallel paired wirings at a high speed by applying double structure to the main line only of the parallel wirings and allocating branch lines. CONSTITUTION:Nets A and B are synthesized for production of a next X. Then main line of the next X is allocated in a wiring area. This synthesized net X is divided into the upper and lower main lines A and B. Finally the branch line is given to each net. As a result, no wiring channel exists between the main lines forming the parallel wirings and therefore the parallel wirings are attained at the minimum interval.

5. 发明专利

JPS6363981A FLIP-FLOP EQUIVALENT CIRCUIT 失效
公开(公告)号：JPS6363981A
公开(公告)日：1988-03-22
申请号：JP20784686
申请日：1986-09-05
申请人： HITACHI LTD
发明人： HIYAMA TORU
IPC分类号： G01R31/28 , G06F11/22 , G06F17/50
摘要： PURPOSE:To form the test pattern in the diagnosis of a logical circuit containing FF at a high speed, by expressing the operation of an FF circuit by a combination circuit and providing an imaginary terminal imparting sequential operation and an element imparting uncertainty. CONSTITUTION:When logical values present at input terminals S, R, CK, D of FF are applied, the logical values outputted to an output terminals Q, -Q are calculated and an initial set logical value is applied to an imaginary terminal SI to form the real value table of an input terminal. A positive phase and inverse phase are taken out from said table with respect to an input pattern, wherein output Q becomes high, in matching relation to the High/Low of an input pin to be inputted to an AND element. The same operation is performed with respect to a pattern wherein the output Q becomes low. When the output is not high and low, an uncertain value is outputted from an element imparting uncertainty. As mentioned above, by providing the imaginary terminal and the uncertainty element, the test pattern in the diagnosis of a logical circuit containing FF is formed at a high speed.

6. 发明专利

JPH11110431A SIGNAL PROPAGATION DELAY TIME CALCULATING METHOD FOR LOGIC CIRCUIT 失效
公开(公告)号：JPH11110431A
公开(公告)日：1999-04-23
申请号：JP27122497
申请日：1997-10-03
申请人： HITACHI LTD , HITACHI INFORMATION TECHNOLOGY
发明人： KUZUSAKA MASAHITO , TAKAGI TOSHIYUKI , KATO NAOKI , HONGO HIDETOMO , ISHII TAKEMOTO , HIYAMA TORU
IPC分类号： H01L21/82 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To make highly accurately performable the signal propagation delay time calculation of a logic circuit such as a semiconductor integrated circuit at a high speed, by avoiding wiring delay time calculation utilizing a high-accuracy calculation model concerning a wiring within the range of an allowable error for the calculated result of signal propagation delay time between flip-flops. SOLUTION: Design information, execution necessity judgement reference value and wiring delay time estimate table are inputted from a design information file (S10). Calculation factors related to the circuit load delay time calculation of a logic element and the wiring delay time calculation of a microbus are extracted from the design information (S11 and S12). The circuit load delay time calculation of the microbus is performed by the high-accuracy calculation model (S13). The estimated wiring delay time of each microbus is found from the extracted calculation factors and the wiring delay time estimate table (S14). The estimated wiring delay time of each microbus is compared with the execution necessity discrimination reference value and when it is less than the execution necessity discrimination reference value, the wiring delay time calculation of that microbus is omitted (S15).

7. 发明专利

JPH10173060A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH10173060A
公开(公告)日：1998-06-26
申请号：JP33338296
申请日：1996-12-13
申请人： HITACHI LTD
发明人： TAKIMOTO MISAO , HIYAMA TORU , SASAKI TETSUO , SUZUKI KATSUKI
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit in which connection information on a common control signal is generated in every region after circuits are arranged by a method wherein all the circuits arranged in the region are searched and the terminal of a circuit, to be distributed, which is connected is detected so as to be connected to a distribution circuit at a second stage. SOLUTION: A logic-information input part 105 and a region input part 103 process inputs from a logic-information file 102 and a logic library 103. Then, a logic information table 112 and a region table 113 are created. A logic- information generation part 108 searches terminals of all circuits inside a region on the basis of the arrangement place of the logic-information generation table 12 and on the basis of the region table 113. Then, whether a distribution circuit must be connected or not is judged. When a circuit, to be distributed, which is arranged inside the region must be connected, the circuit to be distributed is connected to the distribution circuit to which a signal is supplied inside the region.

8. 发明专利

JPH06243199A SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS ELEMENT LAYOUT AND WIRING METHOD 失效
公开(公告)号：JPH06243199A
公开(公告)日：1994-09-02
申请号：JP3098593
申请日：1993-02-19
申请人： HITACHI LTD
发明人： ARIYOSHI SHINICHI , ISHII TAKEMOTO , HIYAMA TORU , SASAKI TETSUO
IPC分类号： H01L21/82 , G06F17/50 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L27/04 , G06F15/60
摘要： PURPOSE:To make a signal delay time (delay) shorter than a reference value by fundamentally inserting a buffer gate having a high driving capability on the preceding-stage element side of the center position of the wiring between the front-stage element and the rear-stage element or widening the wiring width. CONSTITUTION:A buffer gate 6 whose driving capability is higher than that of the preceding-stage element is arranged on the preceding-stage element side. The Figure shows that a circuit load delay dCL6 is longer than a circuit load delay dCL1 of the front-stage element but the delay is shorter by DELTAd6 the point of (wiring length) = 1. Length I and thickness (d) of a wiring having 3-fold width are equal to those of a wiring having one-fold width, and only width m3 of the former is three times as long as width m1 of the latter. A resistance R3 of the wiring having 3-fold width, a resistance R1 of the wiring having one- fold width, a capacitance C3 of the wiring having 3-fold width, and a capacitance C1 of the wiring having one-fold width have the relations R3=R1/3 and C3

9. 发明专利

JPS6461929A POWER WIRING FOR SEMICONDUCTOR GATE ARRAY INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6461929A
公开(公告)日：1989-03-08
申请号：JP21781287
申请日：1987-09-02
申请人： HITACHI LTD
发明人： TAKANASHI YASUO , HIYAMA TORU , SAKATAYA YOSHINORI
IPC分类号： H01L21/822 , G11C11/401 , H01L21/82 , H01L27/04 , H01L27/118
摘要： PURPOSE:To shorten the power wiring length by providing a power wiring route for wirings between a power section supplying different voltages and supply terminals corresponding to each circuit element, and forming a wiring route wherein connections can be made arbitrarily depending on the combination of circuit elements having different supply terminal voltages. CONSTITUTION:In order to design the power wiring of a gate array LSI 1, the type of a cell 2 arranged at each cell on a cell array 3 is determined based on interrelations among the cells 2, and then the number of cell power terminals and their positions by each of power types A to D are obtained. Then the number of power mains required for each of the power types A to D in correspondence with the number of cell power terminals is calculated. A distribution area of cell power terminals is divided equally in the widthwise direction for each of the power types A to D. Then a power main 7 of a power type is assigned to a main area which is closest to the center-of-gravity line in the divided area, and when the positions on a power mains mounting area 5 overlap among power types, adjustments are made by such ways as offsetting the positions of the power mains. Then wirings are connected after selecting a required portion of a fixed route between the power main 7 of each of the power types and the cell power terminals in the divided area. According to the constitution, the wiring length of the gate array LSI comprising a circuit driven by several different power types can be shortened.

10. 发明专利

JPS61110069A Diagnosing system for logical circuit 失效
标题翻译：逻辑电路诊断系统
公开(公告)号：JPS61110069A
公开(公告)日：1986-05-28
申请号：JP23012684
申请日：1984-11-02
申请人： Hitachi Ltd
发明人： HIYAMA TORU , ISHIYAMA TAKASHI , MORIWAKI IKU
IPC分类号： G01R31/28 , G06F11/22 , G06F11/267
CPC分类号： G06F11/221
摘要： PURPOSE:To facilitate the diagnosis with a light detection rate, by performing the diagnosis with the scanning in and out of a switch insertion circuit section after a logical circuit is traced in the fan-in direction to determine the insertion position of a switch from the number of gates. CONSTITUTION:The partial circuit of a large logical circuit is divided into subdivision circuits 1-4. The subdivision circuit 1 is allowed to set data through a switch circuit from alpha, beta and gamma to make the data observable through the switch circuit from FF(a). Likewise, subdivision circuits 2-4 can be diagnosed individually as small circuit using FF (l), (m), (n) and (o) as scan input points and alpha, beta and gamma as scan output points. Upto the present, giant circuits is hard to diagnose because it cannot be handled by the ordinary divided circuit or unavoidably requires huge processing time. But according to this invention, it can be divided into split circuits easy to handle and scanning in or out can be done freely from division points such as alpha, beta and gamma thereby assuring a high diagnosis detection rate and processing speed.
摘要翻译：目的：为了利用光检测率进行诊断，通过在沿风扇方向跟踪逻辑电路之后，通过进入和切出开关插入电路部分进行诊断来确定开关从插入位置门数。构成：大逻辑电路的部分电路分为细分电路1-4。允许细分电路1通过来自α，β和γ的开关电路设置数据，以通过FF（a）通过开关电路观察数据。类似地，细分电路2-4可以使用FF（1），（m），（n）和（o）作为扫描输入点和α，β和γ作为扫描输出点被单独诊断为小电路。到目前为止，巨型电路难以诊断，因为它不能被普通分频电路处理，或者不可避免地需要巨大的处理时间。但是根据本发明，可以将分割电路分为易于处理的分离电路，也可以从α，β和γ等分割点自由地进行扫描，从而确保高的诊断检测率和处理速度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式