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1. 发明专利

JP2004095174A Magnetic recording and reproducing device and circuit used in the same 审中-公开
公开(公告)号：JP2004095174A
公开(公告)日：2004-03-25
申请号：JP2003346661
申请日：2003-10-06
申请人： Hitachi Advanced Digital Inc , Hitachi Ltd , 株式会社日立アドバンストデジタル , 株式会社日立製作所
发明人： SAIKI EISAKU , SUZUMURA SHINTARO , TAKASHI TERUMI , ASHIKAWA KAZUTOSHI , HIROOKA TSUGUYOSHI , MIYAZAWA SHOICHI , MORI MASASHI
IPC分类号： H04N5/781 , G11B5/09 , G11B20/10
摘要： PROBLEM TO BE SOLVED: To realize the acceleration and low power consumption of the entire device by attaining the acceleration and low power consumption of write data transmission between an R/W amplifier and an R/W signal processing circuit. SOLUTION: In the R/W signal processing circuit 3, an interleave write data generation circuit 8 converts inputted write data into write pulse signals C1 and C2 having an interleave relation to each other by alternately distributing sequential bit signals and alternately distributing "1"-bit pulses and transmits the write pulse signals C1 and C2 to the R/W amplifier 2. In the R/W amplifier 2, a synthesis circuit 16 combines the write pulse signals C1 and C2 to restore the original write pulse signal, and a half frequency dividing circuit 12 applies frequency division to the write pulse signal. A read amplifier 11 feeds recording current to an unillustrated magnetic head in accordance with an output signal K of the half frequency dividing circuit 12. This can make the write pulse signal transmit and receive between the R/W signal processing circuit 3 and the R/W amplifier 2 in a low frequency. COPYRIGHT: (C)2004,JPO

2. 发明专利

JP2014155271A Monitoring system for photovoltaic power generation equipment 有权
标题翻译：光伏发电设备监控系统
公开(公告)号：JP2014155271A
公开(公告)日：2014-08-25
申请号：JP2013021122
申请日：2013-02-06
申请人： Hitachi Advanced Digital Inc , 株式会社日立アドバンストデジタル , National Institute Of Advanced Industrial & Technology , 独立行政法人産業技術総合研究所
发明人： NISHIZAWA SADAO , SUZUMURA SHINTARO , ITO TETSUO , YOSHIDA HIDEKI , KASAI YUJI , MURAKAWA MASAHIRO
IPC分类号： H02J13/00 , H01L31/042 , H02J3/38
CPC分类号： H02S50/00 , H02J3/383 , H02J13/0003 , Y02E10/563 , Y02E40/72 , Y04S10/123
摘要： PROBLEM TO BE SOLVED: To improve communication performance between a slave unit and a master unit in a monitoring system for monitoring on the basis of each solar cell panel.SOLUTION: The monitoring system includes a slave unit (4) and a master unit (5). The slave unit (4) superposes to a DC current path a current signal indicative of measurement data individually measured for each of more than one solar cell panel included in a plurality of solar cell panels (P1-P15) constituting a solar cell string (10). The DC current path includes a plurality of power lines (L1-L14), a first trunk power line (21) and a second trunk power line (22). The master unit (5) is coupled to one or both of the first trunk power line (21) and the second trunk power line (22), and receives the measurement data from the slave unit (4).
摘要翻译：要解决的问题：提高监控系统中的从属单元与主单元之间的通信性能，以便在每个太阳能电池板的基础上进行监控。解决方案：监控系统包括从单元（4）和主单元（5 ）。从单元（4）将构成太阳能电池串（10）的多个太阳能电池面板（P1-P15）中包含的多于一个的太阳能电池面板中的每一个单独测量的测量数据表示为DC电流路径）。直流电流路径包括多条电力线（L1-L14），第一干线电力线（21）和第二干线电力线（22）。主单元（5）耦合到第一干线电力线（21）和第二干线电力线（22）中的一个或两个，并且从从单元（4）接收测量数据。

3. 发明专利

JPH07288549A AUTOMATIC GAIN CONTROL SYSTEM 失效
公开(公告)号：JPH07288549A
公开(公告)日：1995-10-31
申请号：JP8048694
申请日：1994-04-19
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： SAIKI EISAKU , MORI MASASHI , SUZUMURA SHINTARO , HIRAI TOMOAKI
IPC分类号： G11B20/10 , H03G3/20 , H03G3/30 , H04B3/04 , H04L25/03 , H04L25/497
摘要： PURPOSE:To provide an automatic gain control system of digital circuit configuration by which high speed and stable level locking is realized. CONSTITUTION:The AGC circuit 41 is provided with a VGA 11 whose gain is controlled variably by a control signal, an EQ 12, an ADC 13, a (1+D) processing circuit 14 implementing limit of a band of a quantization output for PR 4 processing, a VGA controller circuit 25 detecting ah error of a signal 104 after (1+D) processing from an object level and providing error data 117 and error data 118 delayed by one sampling clock respectively, two kinds of D/A converters 16a, 16b converting respectively the two kinds of the error data 117, 118 into respective analog data, an analog adder 26 summing the outputs of the D/A converters 16a, 16b, a multiplier 17 multiplying a prescribed multiple with an analog adder output 125, and an integration device 18 integrating an output signal of the multiplier 17 to produce a control signal 122 for the VGA.

4. 发明专利

JPH05159477A RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPH05159477A
公开(公告)日：1993-06-25
申请号：JP32444591
申请日：1991-12-09
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： MIYAZAWA SHOICHI , SUZUMURA SHINTARO , KARASAWA NORIYUKI , TATEYAMA TSUYOSHI , URAGAMI KEN
IPC分类号： G11B20/14 , H03M9/00
摘要： PURPOSE:To suppress the increase of the circuit configuration and power consumption and to transfer data at high speed by providing a serial/parallel converting means between a recording and reproducing circuit and an encoding/ decoding circuit and making an input/output of the encoding/decoding circuit a parallel data. CONSTITUTION:With regard to recording/reproducing, an input/output data is dealt with as a parallel data signal by providing an S/P circuit 111. At the time of reading, a parallel data 112 obtained by converting a serial data 109 from the recording and reproducing circuit 106 into a prescribed number of bits in conversion bits of a recording code by the S/P circuit 111 is inputted to the encoding/decoding circuit 105. In this circuit 105, the data is parallel- decoded into an NRZ data, and a data 107 processed by further conversion of the NRZ data into 8 bits in order to be easily dealt with by a controller 103. Thus, by handling the data as the parallel data, its operating frequency is lowered to suit a high integrated circuit, thus performing high speed data transfer efficiently without increasing the circuit configuration and power consumption.

5. 发明专利

JPH048016A PHASE LOCKED LOOP CIRCUIT AND RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPH048016A
公开(公告)日：1992-01-13
申请号：JP11120590
申请日：1990-04-26
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： SAIKI EISAKU , SUZUMURA SHINTARO , OI FUKASHI , URAGAMI KEN , KARASAWA NORIYUKI , NAGATA SHUNJI , ARAI SHINICHI
IPC分类号： G11B20/10 , G06F1/04 , H03L7/14
摘要： PURPOSE:To prevent malfunction when a data error such as missing of data exists in a data signal by suppressing charge/discharge based on phase comparison in a phase comparator to a loop filter when a data error takes place in the input data signal. CONSTITUTION:When data missing exists, since a reset signal 44 by an edge detection circuit 43 is not generated till a timing when a TR Q232 goes to a high level, a missing detection signal 25 is outputted. The missing detection signal 25 is outputted till the reset signal 44 is generated by a succeeding data. Thus, a gate 23 of a phase locked loop circuit interrupts an INC signal 6 and a DEC signal 7 being outputs of a phase comparator 1 to suppress an INCG signal 26 and a DECG signal 27.

6. 发明专利

JPH02172071A PHASE LOCKED LOOP CIRCUIT 失效
公开(公告)号：JPH02172071A
公开(公告)日：1990-07-03
申请号：JP32331688
申请日：1988-12-23
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： SAIKI EISAKU , SUZUMURA SHINTARO , KARASAWA TOKUYUKI , KOJIMA SHINICHI , SHIRAISHI KAZUHISA , MINOJIMA SATOSHI
IPC分类号： G11B20/14 , H03L7/08
摘要： PURPOSE:To obtain a readout signal with accurate pulse width without any adjustment by using a delay circuit able to set a dealy with high accuracy, and retarding a VCO signal for a prescribed time with respect to an external input signal. CONSTITUTION:Readout information RD51 is fed to an RD signal generating circuit 1a of a phase comparator 1, an INC (flow-out current of charge pump 2) signal generator 1b and a CK terminal of each DFF of a DEC (drawout current) signal generator 1c, and the leadout signal 57, the INC signal 53 and the DEC signal are raised at the front ridge of the RD51. The delay readout information 58, the DFF 113 and the signal resulting from the signal 58 through delay and polarity inversion are inputted to a 3-input NAND 116, the readout signal is fallen at the front ridge of the signal 58 to obtain the signal 57 with a pulse width of the phase difference between the signals 51 and 58. The circuit 1b falls the INC signal 53 at the front ridge of the delay output 61 and the pulse width is prolonged by that of the signal 57 by a delay tau3. The circuit 1c falls the DEC signal 54 at the trailing edge of the delay output 62 to prolong the pulse width by a delay tau4. Since the relation of tau3=tau4 exists, the pulse width of the signals 57, 53 is set with no adjustment and the width is constant independently of power supply and temperature.

7. 发明专利

JP2001312858A SIGNAL PROCESSING CIRCUIT, AND DIGITAL INFORMATION REPRODUCING/RECORDING DEVICE USING THE SAME 失效
公开(公告)号：JP2001312858A
公开(公告)日：2001-11-09
申请号：JP2000131523
申请日：2000-04-26
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： KATO TAKATOSHI , NISHITANI TAKUJI , YAMAKAWA HIDEYUKI , NARA TAKASHI , NAKAI NOBUAKI , IDE HIROSHI , SUZUMURA SHINTARO , TAKASHI TERUMI
IPC分类号： G11B20/10 , G11B20/14
摘要： PROBLEM TO BE SOLVED: To reduce the data error rate of a signal processing circuit for processing a reproduction signal reproduced from a recording medium in a digital information reproducing device. SOLUTION: This device is provided with an amplitude control signal correcting device 213 for correcting the amplitude control signal controlling the gain of a variable gain amplifier 203 in a signal processing part by using the output value of the maximum likelihood estimation which is performed on the basis of the value of the intermediate stage in a memory path of a maximum likelihood estimating device 207, and a phase control signal correcting device 214 for correcting a phase control signal controlling the phase and frequency of an oscillator 215 supplying the clock to an ADC 205.

8. 发明专利

JPH1011912A SIGNAL REPRODUCER AND PHASE SYNCHRONIZATION CIRCUIT USED THEREFOR 失效
公开(公告)号：JPH1011912A
公开(公告)日：1998-01-16
申请号：JP16807496
申请日：1996-06-28
申请人： HITACHI LTD , HITACHI VIDEO IND INF SYST INC
发明人： MIYAZAWA SHOICHI , SUZUMURA SHINTARO , KATSU HARUTO , NARA TAKASHI , HISADA SHINICHI
IPC分类号： G11B20/14 , H03L7/093
摘要： PROBLEM TO BE SOLVED: To complete the phase pulling of a reading clock in a short time by a method wherein the relative phase difference between the edge phase comparison and the grade phase comparison is adjusted. SOLUTION: A phase synchronization circuit 151 is composed of a grade phase comparison circuit 1511, a D/A converter 1512, a loop filter 1513, a VCO 1514, a lead pulse generating circuit 1515, an edge phase comparator 1516, a charge pump 1517, a switch 1518, a phase deference detection circuit 501 and a variable delay line 502. The circuit 501 detects the phase difference between the edge phase comparison and the grade phase comparison and outputs a control signal s501 in accordance with the output signal a151 of the circuit 1511. The delay line 502 receives the signal s501 and changes its delay value to change the phase of the input lead pulse a501 of the edge phase comparator 1516, so that the steady state phase of a sampling clock a105 which is synchronized with the input lead pulse a501 can be adjusted.

9. 发明专利

JPH08255304A MAGNETIC RECORDING DEVICE 失效
公开(公告)号：JPH08255304A
公开(公告)日：1996-10-01
申请号：JP5924795
申请日：1995-03-17
申请人： HITACHI LTD , HITACHI VIDEO IND INF SYST INC
发明人： HIROOKA TSUGUYOSHI , SAIKI EISAKU , SUZUMURA SHINTARO , TAKASHI TERUMI , NARA TAKASHI
IPC分类号： G11B5/09 , G11B20/10
摘要： PURPOSE: To provide a delay circuit suitable for a recording correction circuit of a magnetic recording circuit by providing the delay circuit, with four delay elements connected in series, thereby keeping the monotonous incrementality, in the change of delay amount. CONSTITUTION: A pattern detecting circuit 11 discriminates that the pattern of data to be actually inputted corresponds to which pattern among stored plural patterns and the data are distributed and outputted to the delay circuit set according to the discriminated result. Then, a delay circuit 15 has, for example, four-stage (n=4) current control delay elements 21 to 24 connected in series, and delay circuits 15 to 17 respectively have four-stage current control delay elements 25 to 28, 29 to 32 similarly. At this time, a current generating circuit 20 respectively supplies current required for realizing the delay time set with respect to the delay circuit 15 to delay elements 24 to 24 included in the circuit 15. Then, when the reference value of the control current with respect to the set delay time is defined as an I, the circuit 20 supplies, for example, the control current of 4I is sent to respective delay elements.

10. 发明专利

JPH08147887A DECODING CIRCUIT AND REPRODUCING DEVICE 失效
公开(公告)号：JPH08147887A
公开(公告)日：1996-06-07
申请号：JP28520694
申请日：1994-11-18
申请人： HITACHI LTD , HITACHI VIDEO IND INF SYST INC
发明人： SAIKI EISAKU , ASHIKAWA KAZUTOSHI , MITA SEIICHI , SUZUMURA SHINTARO , MIYAZAWA SHOICHI , HIROOKA TSUGUYOSHI
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , H03H15/00 , H03H17/00 , H03H21/00 , H03M13/23 , H04B3/04 , H04L25/497 , H03M13/12
摘要： PURPOSE: To enable high-precision data sampling by converting the signals processed by a PR processing means into digital data based on the timing of reference clocks. CONSTITUTION: AGC control is carried out by adjusting the gain of the VGA 6 using sample values converted into digital signals by means of an A/D converter 8. And a PLL controller 16 controls sampling clocks 101 at the time of converting the sample values into digital signals by the A/D converter 8. At the time of accessing, a disk controller 24 instructs to control an actuater controller 26, which calculates the moving speed and the number of moving tracks of the magnetic head using the output signals from a servo positioning detection section and, based on the results of this calculation, drives an actuater 3 through an actuater driver 27 to control the positioning of a magnetic head.

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