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1. 发明专利

JPH08255304A MAGNETIC RECORDING DEVICE 失效
公开(公告)号：JPH08255304A
公开(公告)日：1996-10-01
申请号：JP5924795
申请日：1995-03-17
申请人： HITACHI LTD , HITACHI VIDEO IND INF SYST INC
发明人： HIROOKA TSUGUYOSHI , SAIKI EISAKU , SUZUMURA SHINTARO , TAKASHI TERUMI , NARA TAKASHI
IPC分类号： G11B5/09 , G11B20/10
摘要： PURPOSE: To provide a delay circuit suitable for a recording correction circuit of a magnetic recording circuit by providing the delay circuit, with four delay elements connected in series, thereby keeping the monotonous incrementality, in the change of delay amount. CONSTITUTION: A pattern detecting circuit 11 discriminates that the pattern of data to be actually inputted corresponds to which pattern among stored plural patterns and the data are distributed and outputted to the delay circuit set according to the discriminated result. Then, a delay circuit 15 has, for example, four-stage (n=4) current control delay elements 21 to 24 connected in series, and delay circuits 15 to 17 respectively have four-stage current control delay elements 25 to 28, 29 to 32 similarly. At this time, a current generating circuit 20 respectively supplies current required for realizing the delay time set with respect to the delay circuit 15 to delay elements 24 to 24 included in the circuit 15. Then, when the reference value of the control current with respect to the set delay time is defined as an I, the circuit 20 supplies, for example, the control current of 4I is sent to respective delay elements.

2. 发明专利

JPH09161203A MAGNETIC REPRODUCING DEVICE AND SIGNAL PROCESSING CIRCUIT USING SAME 失效
公开(公告)号：JPH09161203A
公开(公告)日：1997-06-20
申请号：JP31633395
申请日：1995-12-05
申请人： HITACHI LTD , HITACHI VIDEO IND INF SYST INC
发明人： HOTTA RYUTARO , SUZUMURA SHINTARO , HIROOKA TSUGUYOSHI , MIYAZAWA SHOICHI , NARA TAKASHI , TAKASHI TERUMI
IPC分类号： G11B5/02
摘要： PROBLEM TO BE SOLVED: To suppress the distortion of the read-out waveform, to reduce a data error and to increase recording density by always optimally controlling the bias current of a MR head. SOLUTION: A MR bias control circuit 401 is provided in a reading system signal processing circuit. The control circuit 401 detects the deviated direction of the MR bias from read-out data a401, outputs a control signal S401 to a R/W amplifier 402 so as to optimize the bias. In the case, a signal amplitude on the positive side of the data a401 is compared with a signal amplitude on the negative side and a control signal for the bias current is outputted so as to remove the level difference of both amplitudes. Consequently, based on the detected result of the deviation of bias, a read current source circuit 501 in the amplifier 402 is controlled and the MR bias is optimized.

3. 发明专利

JPH08227285A ENLARGEMENT DISPLAY DEVICE 失效
公开(公告)号：JPH08227285A
公开(公告)日：1996-09-03
申请号：JP31560895
申请日：1995-12-04
申请人： HITACHI LTD , HITACHI VIDEO IND INF SYST INC
发明人： MANO HIROYUKI , KONUMA SATOSHI , TSUCHIYA NOBUO , NISHIOKA KIYOKAZU , TAKASHI TERUMI , JINUSHI MASAHIRO
IPC分类号： H04N5/262 , G09G3/20 , G09G5/00 , G09G5/26 , G09G5/391
摘要： PURPOSE: To convert display capacity so as to hold natural quality of an image and is suitable for a display device. CONSTITUTION: For the display device 2 fetching the display data by a clock pulse, a display memory address generation part 8 or a display device interface 4 controls the display data read out of a display memory 6 or the clock pulse imparted to the display device according to the control of a display conversion control part 9. The display conversion control part 9 controls so that the display data of the number of dots B are fetched to the display device 2 according to the number of dots A of an image by the display data stored in the display memory 6 and the number of dots B displayed by the display device 2.

4. 发明专利

JPH0845010A MAGNETIC RECORDING AND REPRODUCING DEVICE AND CIRCUIT USED FOR THE SAME 失效
公开(公告)号：JPH0845010A
公开(公告)日：1996-02-16
申请号：JP12851095
申请日：1995-05-26
申请人： HITACHI LTD , HITACHI VIDEO IND INF SYST INC
发明人： SAIKI EISAKU , SUZUMURA SHINTARO , TAKASHI TERUMI , ASHIKAWA KAZUTOSHI , HIROOKA TSUGUYOSHI , MIYAZAWA SHOICHI , MORI MASASHI
IPC分类号： G11B5/09 , G11B20/10
摘要： PURPOSE:To operate the device at high speed with low power consumption as a whole by transmitting write data between an R/W amplifier and an R/W signal processing circuit at high speed with low power consumption. CONSTITUTION:In the R/W signal processing circuit 3, write data inputted is converted into write pulse signals C1 and C2 in interleaved relation with each other by distributing alternately bit signals in order and distributing alternately '1'-bit pulses by an interleaving write data generating circuit 8, and is transmitted to the R/W amplifier 2. In the R/W amplifier 2, these write pulse signals C1 and C2 are synthesized to be restored to their original write pulse signal by a synthesizing circuit 16, and is frequency-divided by a 1/2 frequency division circuit 12. A recording current is supplied to a magnetic head which is not shown in the figure in response to an output signal K of this 1/2 frequency division circuit 12 by the read amplifier 11. By this method, the write pulse signal can.be delivered in a low frequency between the R/W signal processing circuit 3 and the R/W amplifier 2.

5. 发明专利

JP2001332035A DATA SYNCHRONIZING SIGNAL DETECTOR, SIGNAL PROCESSOR USING THE SAME, INFORMATION RECORDING AND REPRODUCING DEVICE PROVIDED WITH THESE, AND DATA SYNCHRONIZING SIGNAL DETECTION METHOD AND INFORMATION RECORDING MEDIUM USED FOR THE METHOD 失效
公开(公告)号：JP2001332035A
公开(公告)日：2001-11-30
申请号：JP2000148835
申请日：2000-05-19
申请人： HITACHI LTD
发明人： WATABE YOSHIHISA , TAKASHI TERUMI
IPC分类号： G11B20/14 , G11B5/012 , G11B5/09 , G11B20/10 , G11B20/18 , G11B27/10 , G11B27/30 , H04L1/00 , H04L7/04 , H04L7/08
摘要： PROBLEM TO BE SOLVED: To provide a data synchronizing signal detector with simple configuration which detects a data synchronizing signal with little detection error. SOLUTION: A discrimination means 11 for data and a discrimination means 12 for synchronizing signal are provided as a data discrimination means, the detection of the data synchronizing signal is performed to the bit string being discriminated from the output of the discrimination means 12 for synchronizing signal and data demodulation is performed to the bit string being discriminated from the output of the discrimination means 11 for data, thus the discrimination of the bit is performed in an optimized form suitable for each of the discrimination of the data synchronizing signal, the data synchronizing signal detection, and the demodulation of the reproduction. Thereby, the capability of detection of the data synchronizing signal can be improved, while maintaining the data discrimination performance. For the optimization at this time, a maximum likelihood decoder is used as each of discrimination means of the discrimination means 11 for data and the discrimination means 12 for synchronizing signal, and the optimization of the number of states, the number of passes of state transition and pass memory length is performed.

6. 发明专利

JP2000322035A LIQUID CRYSTAL DISPLAY DEVICE 失效
公开(公告)号：JP2000322035A
公开(公告)日：2000-11-24
申请号：JP2000112302
申请日：2000-04-13
申请人： HITACHI LTD
发明人： TATEUCHI TSUGUJI , MANO HIROYUKI , TAKASHI TERUMI
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
摘要： PROBLEM TO BE SOLVED: To prevent a generation of a flicker, and capable of displaying a medium tone. SOLUTION: Character data read out from a display memory 10 become display data 9 in a display data generating circuit 6, and are supplied to a gate circuit 17. A count valve for a frame pulse signal 18 on a frame counter 14 and a count valve for a line signal on a line counter 15 are supplied to a display control circuit 16, and a display prohibiting signal 21 is generated using an attribute signal 20 from an attribute memory 11. The gate circuit 17 prohibits the display data 9 from passing at lines with a prescribed interval on one frame, and prohibits different lines from passing for each frame.

7. 发明专利

JP2000048490A SIGNAL PROCESSOR AND DATA RECORDING/REPRODUCING DEVICE INSTALLED WITH THE PROCESSOR 失效
公开(公告)号：JP2000048490A
公开(公告)日：2000-02-18
申请号：JP13969899
申请日：1999-05-20
申请人： HITACHI LTD
发明人： TAKASHI TERUMI , MITA SEIICHI , SAITO ATSUSHI
IPC分类号： G11B20/10 , G11B20/18
摘要： PROBLEM TO BE SOLVED: To improve data reliability at a data recovery time by providing a storage means for storing a reproducing signal and reproducing the data with a different control parameter based on the stored reproducing signal. SOLUTION: A selection circuit 165 selects one of a phase error signal, a complementary frequency error and an amplitude error by a conditional selection signal to output it to a comparator 166 as the error signal. A delay circuit 167 stores the output of the comparator 166 at every sample, and a decision circuit 168 judges the lapse of time of the error signal from the output of the delay circuit 167 to assert a switch condition. For instance, when a phase error or the amplitude error of a threshold or above is continued, the decision circuit 168 detects the continuance of '1' in the outputs of the delay circuit 167 to make the switch condition active. Further, when the complementary frequency error is different to the threshold or above, the decision circuit 168 makes similarly the switch condition active. This switch condition is imparted to a microcomputer through a register.

8. 发明专利

JPH09251716A SIGNAL PROCESSOR 失效
公开(公告)号：JPH09251716A
公开(公告)日：1997-09-22
申请号：JP5714096
申请日：1996-03-14
申请人： HITACHI LTD
发明人： WATABE YOSHIHISA , TAKASHI TERUMI
IPC分类号： G11B20/10 , G11B20/12 , G11B20/14
摘要： PROBLEM TO BE SOLVED: To improve medium storage capacity by reducing a circuit delay absorption pattern. SOLUTION: A reproducing system circuit including an A/D converter 12, an equalizer 13, a data distinguisher/demodulator 14, etc., operated by a reproducing clock 705 obtained from a read-out input signal 701 is provided with a clock reproducing circuit 16 latching and generating the reproducing clock 705 with a clock hold signal 704 as a trigger and a fixed pattern generation circuit 31 generating a fixed pattern required for the equalizer 13, etc., and the continuous operation of the reproducing system circuit is made possible without the reproducing clock 705 obtained from the read-out input signal 701 and the fixed pattern, etc., and by recording/reproducing continuous data on a continuous sector on a disk like medium at intervals, the circuit delay absorption pattern in the sector is eliminated. Further, two channels or more of these reproducing system circuits are provided, and respective channels are operated alternately every continuous sector, and the continuous data are recorded/ reproduced on the continuous sector without the circuit delay absorption pattern.

9. 发明专利

JPH09237069A LIQUID CRYSTAL DISPLAY DEVICE 失效
公开(公告)号：JPH09237069A
公开(公告)日：1997-09-09
申请号：JP28056496
申请日：1996-10-23
申请人： HITACHI LTD
发明人： FUJISAWA KAZUHIRO , MANO HIROYUKI , TAKASHI TERUMI
IPC分类号： G02F1/133 , G09G3/36
摘要： PROBLEM TO BE SOLVED: To eliminate the need for revising a circuit whenever the number of horizontal dots of a display input signal are revised by displaying the display signal of the number of optional horizontal dots within the range of row memory capacity. SOLUTION: When a display timing signal 3 becomes a 'low' level, a count means 32 stops count-up operation, and a horizontal display dot number latch means 34 latches the number of horizontal display dots 33 when a rise of a horizontal synchronizing signal 4 is inputted, and outputs the number of latch horizontal display dots 35 to a comparison means 36 until the rise of the next horizontal synchronizing signal 4 is inputted, that is, for the period displaying the output data 20. When a read-out address 17 is equalized with the number of latch horizontal display dots 35, the latch horizontal display dots 35 and the read-out address 17 become equal, and the comparison means 36 outputs a low level signal to a comparison output 37 to reset a read-out address generation means 28. Thus, the read-out of three times or above are performed from a RAM 7 for one horizontal period.

10. 发明专利

JPH09205362A PHASE SYNCHRONIZATION DEVICE AND ITS ACTUAL DEVICE 失效
公开(公告)号：JPH09205362A
公开(公告)日：1997-08-05
申请号：JP1154496
申请日：1996-01-26
申请人： HITACHI LTD
发明人： TAKASHI TERUMI , HIRANO AKIHIKO
IPC分类号： G11B20/10 , H03L7/093
摘要： PROBLEM TO BE SOLVED: To minimize the increase in a phase synchronization period due to circuit characteristics fluctuation by adjusting a phase synchronization response with respect to an input signal to have a predetermined phase synchronization response. SOLUTION: A step response generating circuit 8 generates a predetermined step response with respect to an input signal and provides a response with a trigger signal (trig) as outputs. A reference synchronization response generating circuit 9 uses the trigger signal (trig) as a trigger to generate a predetermined synchronization response waveform (object response waveform). A subtractor 10 calculates an error between the object response waveform and a synchronization response generated by the phase synchronization device and calculates the adjustment amount minimizing the error by an adjustment amount decision circuit 11. Then a gain setting circuit 12 outputs a decided adjustment amount to V/I conversion circuits 2, 3 to adjust the gain of the phase synchronization device and the cut-off frequency. Furthermore, a selection circuit 13 revises the number of loop orders of the phase synchronization device by an adjustment mode signal (mode) to adjust the synchronization response of the phase synchronization device.

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