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1. 发明专利

JP2004095174A Magnetic recording and reproducing device and circuit used in the same 审中-公开
公开(公告)号：JP2004095174A
公开(公告)日：2004-03-25
申请号：JP2003346661
申请日：2003-10-06
申请人： Hitachi Advanced Digital Inc , Hitachi Ltd , 株式会社日立アドバンストデジタル , 株式会社日立製作所
发明人： SAIKI EISAKU , SUZUMURA SHINTARO , TAKASHI TERUMI , ASHIKAWA KAZUTOSHI , HIROOKA TSUGUYOSHI , MIYAZAWA SHOICHI , MORI MASASHI
IPC分类号： H04N5/781 , G11B5/09 , G11B20/10
摘要： PROBLEM TO BE SOLVED: To realize the acceleration and low power consumption of the entire device by attaining the acceleration and low power consumption of write data transmission between an R/W amplifier and an R/W signal processing circuit. SOLUTION: In the R/W signal processing circuit 3, an interleave write data generation circuit 8 converts inputted write data into write pulse signals C1 and C2 having an interleave relation to each other by alternately distributing sequential bit signals and alternately distributing "1"-bit pulses and transmits the write pulse signals C1 and C2 to the R/W amplifier 2. In the R/W amplifier 2, a synthesis circuit 16 combines the write pulse signals C1 and C2 to restore the original write pulse signal, and a half frequency dividing circuit 12 applies frequency division to the write pulse signal. A read amplifier 11 feeds recording current to an unillustrated magnetic head in accordance with an output signal K of the half frequency dividing circuit 12. This can make the write pulse signal transmit and receive between the R/W signal processing circuit 3 and the R/W amplifier 2 in a low frequency. COPYRIGHT: (C)2004,JPO

2. 发明专利

JP2000227893A STORAGE DEVICE 失效
公开(公告)号：JP2000227893A
公开(公告)日：2000-08-15
申请号：JP37049899
申请日：1999-12-27
申请人： HITACHI LTD
发明人： NAGAE YUKARI , MIYAZAWA SHOICHI , WATANABE KUNIO , KOJIMA SHINICHI , SHIDA KOJI
IPC分类号： G06F1/32 , G06F13/10
摘要： PROBLEM TO BE SOLVED: To provide a storage device capable of reducing power consumption in a command waiting state from an outside processor by controlling a system to a low power consumption mode smaller than power consumption at an activation mode in response to the completion of command execution. SOLUTION: In a power consumption control circuit 2, an RS flip flop 29 is set from chip selection and write strobe through a gate 26 and a gate 28. The output of a flip flop 32 operates an inner clock through a gate 33 and releases a low power consumption mode. When the command proceessings of respective I/O control circuits are terminated, a command termination signal through the gate is inputted to the gate 38 of the power consumption control circuit 2 and the RS flip flop 29 is reset through a gate 39 and a flip flop 40. The output of the gate 29 controls the gate 33 through the flip flops 31 and 32, stops the inner clock and returns the system to the low power consumption mode.

3. 发明专利

JP2000227892A PERIPHERAL CONTROLLER AND SCSI BUS CONTROLLER 失效
公开(公告)号：JP2000227892A
公开(公告)日：2000-08-15
申请号：JP37050099
申请日：1999-12-27
申请人： HITACHI LTD
发明人： NAGAE YUKARI , MIYAZAWA SHOICHI , WATANABE KUNIO , KOJIMA SHINICHI , SHIDA KOJI
IPC分类号： G06F1/32 , G06F13/10 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To provide a peripheral controller such as a peripheral control sling LSI which can reduce power consumption as much as possible while the burden of an outer processor is reduced by controlling the power consumption of the peripheral controller in accordance with the output of an activation start detection means and an activation termination detection means. SOLUTION: A power consumption control circuit 2 detects activation and supplies inner clocks to register groups 8-10 and I/O control circuits 11-13. The register groups 8-10 and the I/O control circuits 11.13 become operation possible states and commands held by a latch 6 are transferred to command registers in the respective register groups 8-10. When the command processing is terminated, the I/O control circuits 11-13 output command termination signals to a NOR gate 1 as an activation termination detection means and the NOR gate 1 outputs are inputted to the power consumption control circuit 2. The power consumption control circuit 2 stops again the inner clock outputs and returns to a low power consumption mode.

4. 发明专利

JPH1011912A SIGNAL REPRODUCER AND PHASE SYNCHRONIZATION CIRCUIT USED THEREFOR 失效
公开(公告)号：JPH1011912A
公开(公告)日：1998-01-16
申请号：JP16807496
申请日：1996-06-28
申请人： HITACHI LTD , HITACHI VIDEO IND INF SYST INC
发明人： MIYAZAWA SHOICHI , SUZUMURA SHINTARO , KATSU HARUTO , NARA TAKASHI , HISADA SHINICHI
IPC分类号： G11B20/14 , H03L7/093
摘要： PROBLEM TO BE SOLVED: To complete the phase pulling of a reading clock in a short time by a method wherein the relative phase difference between the edge phase comparison and the grade phase comparison is adjusted. SOLUTION: A phase synchronization circuit 151 is composed of a grade phase comparison circuit 1511, a D/A converter 1512, a loop filter 1513, a VCO 1514, a lead pulse generating circuit 1515, an edge phase comparator 1516, a charge pump 1517, a switch 1518, a phase deference detection circuit 501 and a variable delay line 502. The circuit 501 detects the phase difference between the edge phase comparison and the grade phase comparison and outputs a control signal s501 in accordance with the output signal a151 of the circuit 1511. The delay line 502 receives the signal s501 and changes its delay value to change the phase of the input lead pulse a501 of the edge phase comparator 1516, so that the steady state phase of a sampling clock a105 which is synchronized with the input lead pulse a501 can be adjusted.

5. 发明专利

JPH09245441A READ/WRITE CIRCUIT 失效
公开(公告)号：JPH09245441A
公开(公告)日：1997-09-19
申请号：JP6935797
申请日：1997-03-24
申请人： HITACHI LTD
发明人： MIYAZAWA SHOICHI , HOTTA RYUTARO , HASE KENICHI , KAWAMURA TETSUSHI
IPC分类号： G11B20/14 , H03M7/00
摘要： PROBLEM TO BE SOLVED: To meet high-speed data transfer with small power consumption by providing a circuit using a BiCMOS process wherein bipolar and CMOS transistors are provided mixedly. SOLUTION: A read/write circuit constructed on one chip is equipped with VCO 1, a T-I converter 2, a charge pump 3, a phase comparator 4, a frequency comparator 5, a synchronization circuit 6, a phase synchronization circuit 7, a (2, 7) decoder 8, 8 (2, 7) encoder 9, an AM generation circuit 10 and a write compensation circuit 11. Each circuit is constructed on the same semiconductor chip including a BiCMOS circuit wherein a bipolar transistor and CMOSFET are provided mixedly, and an input stage of the VCO 1 is constructed of MOSFET having a high input resistance, while an oscillating part of the VCO 1 includes the bipolar transistor operating at a high speed.

6. 发明专利

JPH0944998A REPRODUCED SIGNAL PROCESSING CIRCUIT AND MAGNETIC RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPH0944998A
公开(公告)日：1997-02-14
申请号：JP19750495
申请日：1995-08-02
申请人： HITACHI LTD
发明人： HIROOKA TSUGUYOSHI , MIYAZAWA SHOICHI , HOTTA RYUTARO , ISHIDA YOSHITERU , KATSU HARUTO , NARA TAKASHI , TAKASHI TERUMI
IPC分类号： G11B20/10 , H03H21/00 , H04B3/06 , H04L25/03
摘要： PROBLEM TO BE SOLVED: To obtain a signal processing circuit for magnetic recording device having a small circuit scale and low power consumption even though the circuit is of a PR10, system. SOLUTION: At the time of a non-reproducing, an amplitude control is performed by controlling a VGA 2 based on the output of an LPF 3 by an amplitude control circuit (a) 9. At the time of a reproducing, an amplitude control circuit (b) 10 controls an amplitude by utilizing a waveform equalizer 5 based on the output of the equalizer 5. In the case a transvesal type filter is used as the waveform equalizer 5, the amplitude is controlled by changing the coefficient of a center tap. Moreover, this circuit may be constituted so that a fixed gain is only applied to the VGA by eliminating the amplitude control circuit (a) 9. Since it is not necessary that a control amouns is converted from a digital value into an analog value in the amplitude control circuit (b) 10, the circuit scale and power consumption of the circuit are remarkably reduced.

7. 发明专利

JPH08321142A METHOD FOR JUDGING CORRECTNESS OF SERVO SECTOR ADDRESS, DISK-TYPE STORAGE, AND ITS CONTROL DEVICE 失效
公开(公告)号：JPH08321142A
公开(公告)日：1996-12-03
申请号：JP12672995
申请日：1995-05-25
申请人： HITACHI LTD
发明人： TSUNODA MOTOYASU , MIYAZAWA SHOICHI , OGAWA HITOSHI , NAKAI KOSUKE , NISHINA MASATOSHI , YAMAMOTO KATSUMI
IPC分类号： G11B20/12 , G11B19/02 , G11B20/18 , G11B21/10 , G11B27/10
摘要： PURPOSE: To improve the reliability of a system by comparing an address read from a servo sector with a servo sector address which is predicted from the address and generating a required data sector address. CONSTITUTION: A CPU 11 calculates an address on a recording medium requested from a computer 15 and reports it to a control part 8. The control part 8 obtains a data sector address from the read signal and sends it to a control part 9. At the same time, a signal for following a head 6 is sent to a driver 5, thus enabling the head 6 to be moved to a target position and an amplifier 4 to amplify a signal read by the head 6 and output it to a device 3. The device 3 classifies data and sends it to the control part 9. The control part 9 judges whether the transmitted data are proper or not and sends the conforming data to a control part 12 and a control part 10. The control part 12 sends data whose error is corrected to a computer 15 by the control part 10 via a buffer 13 and a control part 14.

8. 发明专利

JPH08287607A MAGNETIC DISK DEVICE 失效
公开(公告)号：JPH08287607A
公开(公告)日：1996-11-01
申请号：JP8960995
申请日：1995-04-14
申请人： HITACHI LTD
发明人： KATSU HARUTO , MIYAZAWA SHOICHI , HIROOKA TSUGUYOSHI , TAKASHI TERUMI , NARA TAKASHI
IPC分类号： G11B20/10 , G11B20/18
摘要： PURPOSE: To compensate circuit loss fluctuation in an analog waveform equalizer by comparing the peak value of a reproduced data signal inputted to an A/D converter with an expected value and correcting the A/D conversion coefficient. CONSTITUTION: Power consumption in a read system circuit is reduced by using the waveform equalizer 8 of analog system. At this time, a peak value detection circuit 15 detects a signal value in a peak point of a waveform of the reproduced data signal from a PR processor 9. Whenever a mean value calculation circuit 16 detects a prescribed number of peak signals, it calculates the mean value M of the peak signal values. An operation circuit 17 compares the expected value Y of the peak signal value stored beforehand in a register 18 with the mean value M, and corrects a reference voltage V imparted to the A/D converter 10 based on the comparison to keep it to a voltage hold circuit 19. The A/D converter 10 converts the reproduced data signal from the PR processor 9 by the corrected reference voltage V, and eliminates the loss fluctuation in the analog waveform equalizer 8 to send it to a viterbi decoder 11.

9. 发明专利

JPH08147887A DECODING CIRCUIT AND REPRODUCING DEVICE 失效
公开(公告)号：JPH08147887A
公开(公告)日：1996-06-07
申请号：JP28520694
申请日：1994-11-18
申请人： HITACHI LTD , HITACHI VIDEO IND INF SYST INC
发明人： SAIKI EISAKU , ASHIKAWA KAZUTOSHI , MITA SEIICHI , SUZUMURA SHINTARO , MIYAZAWA SHOICHI , HIROOKA TSUGUYOSHI
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , H03H15/00 , H03H17/00 , H03H21/00 , H03M13/23 , H04B3/04 , H04L25/497 , H03M13/12
摘要： PURPOSE: To enable high-precision data sampling by converting the signals processed by a PR processing means into digital data based on the timing of reference clocks. CONSTITUTION: AGC control is carried out by adjusting the gain of the VGA 6 using sample values converted into digital signals by means of an A/D converter 8. And a PLL controller 16 controls sampling clocks 101 at the time of converting the sample values into digital signals by the A/D converter 8. At the time of accessing, a disk controller 24 instructs to control an actuater controller 26, which calculates the moving speed and the number of moving tracks of the magnetic head using the output signals from a servo positioning detection section and, based on the results of this calculation, drives an actuater 3 through an actuater driver 27 to control the positioning of a magnetic head.

10. 发明专利

JPH0878982A AGC AMPLIFIER CONTROL CIRCUIT 失效
公开(公告)号：JPH0878982A
公开(公告)日：1996-03-22
申请号：JP21558294
申请日：1994-09-09
申请人： HITACHI LTD
发明人： WATANABE KUNIO , MIYAZAWA SHOICHI , HOTTA RYUTARO , HASE KENICHI , ISHIDA YOSHITERU , NARA TAKASHI , TAKASHI TERUMI
IPC分类号： H03G3/20 , H03G3/30 , H03G5/16
摘要： PURPOSE: To constantly maintain the output of a digital equalizer to an arbitrary value by controlling the slice level of an analog AGC loop so that the output value of the digital equalizer may be the expected value of a maximum decoding in the analog AGC loop. CONSTITUTION: When a signal DEQOUT is lower than the output expected value VTH of the output DEQOUT of a digital equalizer 14, a digital detector 16 compares the expected value VTH and the signal DEQOUT and outputs a signal UP when the signal DEQOUT is low. An MPU 17 increases the value of a slice level setting register 18 according to this output. Therefore, the DAC of an analog AGC control 19 increases a slice level VSL for discharge and a slice level VSH for charge, performs discharge/charge operations by higher threshold and lowers VAGC. As a result, the voltage difference of control voltage VAGC and VREF becomes large and an AGC amplifier 11 increases the the amplitude control of an analog AGC loop. The control is repeated so that the expected value VTH and the value of the signal DEQOUT may be equal.

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