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1. 发明专利

JPH1011912A SIGNAL REPRODUCER AND PHASE SYNCHRONIZATION CIRCUIT USED THEREFOR 失效
公开(公告)号：JPH1011912A
公开(公告)日：1998-01-16
申请号：JP16807496
申请日：1996-06-28
申请人： HITACHI LTD , HITACHI VIDEO IND INF SYST INC
发明人： MIYAZAWA SHOICHI , SUZUMURA SHINTARO , KATSU HARUTO , NARA TAKASHI , HISADA SHINICHI
IPC分类号： G11B20/14 , H03L7/093
摘要： PROBLEM TO BE SOLVED: To complete the phase pulling of a reading clock in a short time by a method wherein the relative phase difference between the edge phase comparison and the grade phase comparison is adjusted. SOLUTION: A phase synchronization circuit 151 is composed of a grade phase comparison circuit 1511, a D/A converter 1512, a loop filter 1513, a VCO 1514, a lead pulse generating circuit 1515, an edge phase comparator 1516, a charge pump 1517, a switch 1518, a phase deference detection circuit 501 and a variable delay line 502. The circuit 501 detects the phase difference between the edge phase comparison and the grade phase comparison and outputs a control signal s501 in accordance with the output signal a151 of the circuit 1511. The delay line 502 receives the signal s501 and changes its delay value to change the phase of the input lead pulse a501 of the edge phase comparator 1516, so that the steady state phase of a sampling clock a105 which is synchronized with the input lead pulse a501 can be adjusted.

2. 发明专利

JPH11120503A MAGNETIC STORING SIGNAL PROCESSING/CONTROL CIRCUIT 失效
公开(公告)号：JPH11120503A
公开(公告)日：1999-04-30
申请号：JP27871097
申请日：1997-10-13
申请人： HITACHI LTD
发明人： HISADA SHINICHI
IPC分类号： G06F3/06 , G11B5/02
摘要： PROBLEM TO BE SOLVED: To reduce the number of parts, to improve mounting density, to easily accelerate a data transfer and to reduce a signal noise. SOLUTION: A semiconductor integrated signal processing/control circuit is constituted so that a format circuit 71 generating the data according to a format of a storage medium 11 based on a signal supplied from a host computer 20, an error correction circuit 72 adding an error correction code to the write data and checking/correcting the correction code of the read data, a signal processing circuit 73 modeming the read/write data by a modulation system such as an NRZI system, etc., and generating a reading clock signal and a writing clock signal, an interface circuit 75 interfacing the signal between a buffer memory 74 providing a temporary storage area at a data transfer time and the host computer 20 and a microprocessor 77 controllably controlling these circuits are formed on a semiconductor chip.

3. 发明专利

JPH076093A STORAGE CONTROLLER 失效
公开(公告)号：JPH076093A
公开(公告)日：1995-01-10
申请号：JP14325193
申请日：1993-06-15
申请人： HITACHI LTD
发明人： HISADA SHINICHI , URAGAMI KEN
IPC分类号： G06F12/08 , G06F12/12 , G06F13/10 , G06F13/38
摘要： PURPOSE:To improve the throughput of a host computer by increasing the hit rate of a cache while performing data transfer between a disk storage device such as an HDD and the host computer at a high speed. CONSTITUTION:The storage controller 1 which is interposed between the host computer 100 and disk storage device 200 and controls the data transfer between the both is provided with a 1st buffer memory 4 which stores transfer data in the unit of sector and a 2nd buffer memory 7 which forms the cache memory. Consequently, while a large amount of data are transferred between the external storage device 200 such as the HDD and the host 100 at a high speed, the hit rate of the cache is increased to improve the throughput of the host 100.

4. 发明专利

JPH038015A DISK DRIVE CONTROLLER 失效
公开(公告)号：JPH038015A
公开(公告)日：1991-01-16
申请号：JP14211589
申请日：1989-06-06
申请人： HITACHI LTD
发明人： IZEKI TOSHIYUKI , HISADA SHINICHI , MIYAZAWA SHOICHI , KURIHARA HIROSHI
IPC分类号： G06F3/06 , G06F5/06 , G06F5/12
摘要： PURPOSE:To obtain a disk drive controller, which can transfer data without interposing a CPU, by providing a counting means and a detecting means and prohibiting the prescribed transfer of the data when a transfer prohibiting signal is outputted from the detecting means. CONSTITUTION:A counting means 2 is provided to respectively input a host transfer end signal 11, which is obtained when the data for one sector are finished to be transferred between a host and a buffer memory 23, and a drive transfer end signal 12 which is obtained when the data for one sector are finished to be transferred between a disk drive device and the memory 23, to count-up (or count-down) contents for each input of the signal 11 and to count- down (or count-up) for each input of the signal 12. Then, a detecting means 4 is provided to detect whether the contents of the means 2 are a prescribed value or not and to output a transfer prohibiting signal 15 when it is detected that the contents are the prescribed value. When the signal 15 is outputted, the data transfer from the memory 23 to the host and the data transfer from the memory 23 to the disk drive device are prohibited. Accordingly, there is no burden for CPU processing.

5. 发明专利

JPH0832449A FREQUENCY SYNTHESIS CIRCUIT 失效
公开(公告)号：JPH0832449A
公开(公告)日：1996-02-02
申请号：JP16156094
申请日：1994-07-13
申请人： HITACHI LTD
发明人： HISADA SHINICHI
IPC分类号： H03L7/18
摘要： PURPOSE:To extend stably and considerably an output frequency variable range of the frequency synthesis circuit employing a phase control loop by varying individually a frequency division ratio of a variable frequency divider frequency- dividing an output frequency of a voltage controlled oscillator(VCO) and an oscillated frequency region of the VCO through a control register provided independently. CONSTITUTION:A phase control loop consisting of a VCO 11, variable frequency dividers 12, 13, a phase comparator 14 and a charge pump circuit 15 is formed to provide an output of a clock signal whose frequency is fo depending on a reference clock signal fs given externally and a frequency division ratio of the frequency dividers 12, 13. Thus, the frequency division ratio of the frequency dividers 12, 13 is independently and digitally varied by using control registers 21, 22. Set data Dm, Dn, Ds are given to the control registers 21, 22 via common buses 30, 20. Thus, an output frequency fo of the frequency synthesis circuit 1 is varied optionally externally.

6. 发明专利

JPH05166303A DATA INPUT DEVICE 失效
公开(公告)号：JPH05166303A
公开(公告)日：1993-07-02
申请号：JP35276791
申请日：1991-12-16
申请人： HITACHI LTD
发明人： HISADA SHINICHI , OSAKI KATSUMI , URAGAMI KEN
IPC分类号： G11B20/18
摘要： PURPOSE:To simplify the constitution of the device and to read out data at an optimum timing by detecting two taps of maximum and minimum delays for which an error is first detected based on an error detecting signal. CONSTITUTION:A clock pulse C1 is formed by a phase locked loop PLL by the delay signal D6 of the middle point tap of a delay line for receiving input data D1 from a hard disk memory. A delay signal D3 from the tap almost in the center of the delay line is fetched by a selector synchronizing with this clock pulse C1 and it is supplied to an error detection circuit ECC. Based on its error signal, the increment or the decrement of a selector control circuit INDEC is operated and the two taps of the maximum and minimum delays for which the error is first detected are detected. Thus, the optimum timing is provided for the data D1.

7. 发明专利

JPH0337747A STORAGE DEVICE CONTROLLER, DISK CACHE METHOD AND DISK CACHE SYSTEM 失效
公开(公告)号：JPH0337747A
公开(公告)日：1991-02-19
申请号：JP17330889
申请日：1989-07-05
申请人： HITACHI LTD
发明人： HISADA SHINICHI , IZEKI TOSHIYUKI , MIYAZAWA SHOICHI , KURIHARA HIROSHI
IPC分类号： G06F12/08 , G06F3/06
摘要： PURPOSE:To form the disk cache system provided with both a high speed property of an SRAM and a large capacity property of a DRAM by using simultaneously the DRAM and the SRAM. CONSTITUTION:A storage device controller 1 is provided with a DRAM control part 5 and an SRAM control part 6, and both the RAM control parts 5, 6 execute an access to a DRAM 3 and an SRAM 4, respectively in accordance with an instruction of other control part 10. A memory address of each RAM 3, 4 in such a case is supplied from a memory address control part 8. Also, a data control part 9 converts mutually parallel data of a RAM and serial data of an auxiliary storage device, or switches and connects a data bus of the RAM to the auxiliary storage device side or a microprocessor 2 side. This storage device controller 1 is provided between a host computer and the auxiliary storage device. In such a way, a disk cache system provided with both a large capacity property of the DRAM 3 and a high speed property of the SRAM 4 can be constructed.

8. 发明专利

JPH02207363A DATA TRANSFER SYSTEM, DEVICE CONTROLLER, AND MEMORY CONTROLLER 失效
公开(公告)号：JPH02207363A
公开(公告)日：1990-08-17
申请号：JP2939889
申请日：1989-02-08
申请人： HITACHI LTD
发明人： IZEKI TOSHIYUKI , MIYAZAWA SHOICHI , HISADA SHINICHI , KURIHARA HIROSHI
IPC分类号： G06F13/38 , G06F13/28
摘要： PURPOSE:To perform data transfer between an I/O device and a memory with control signals fewer than ever by applying control so as to perform the data transfer synchronizing with a transfer timing signal. CONSTITUTION:A bus master 2, a device controller 3, and a memory controller 5 are provided. A selector 33 selects a processing to output read/write control signals to a device as it is, or the processing to output the signal setting the read control signal as the write control signal and the write control signal as the read control signal. A register 34 which stores the above selection information stores information by the write operation of an MPU 1, and a selector 51 is controlled by a memory access permission signal at the memory controller. In such a way, the data transfer can be performed between the I/O device and the memory or between the I/O devices mutually by the same control signal and with the same timing.

9. 发明专利

JPH0251724A DISK CONTROLLER 失效
公开(公告)号：JPH0251724A
公开(公告)日：1990-02-21
申请号：JP20200188
申请日：1988-08-15
申请人： HITACHI LTD
发明人： MIYAZAWA SHOICHI , IZEKI TOSHIYUKI , HISADA SHINICHI , OTA HIROBUMI
IPC分类号： G06F3/06
摘要： PURPOSE:To decrease the number of component chips of a disk controller and at the same time to improve the flexibility for extension of a function by providing a multiplexer and a switch control means into a file data processor and therefore ensuring the effective use of the area of a data buffer RAM. CONSTITUTION:The outputs of the buffer pointers 10 and 11 and the address output of a microprocessor MPU are selected by a switch control part 7 and a multiplexer 8 for output addresses MA0-15 to be applied to a data buffer RAM. Then the data input/output route led from the MPU or an input/output route used for read/write to a disk is connected to an input/output route for the buffer RAM via the multiplexer 8, etc. Thus said two routes are connected to each other via the part 7, etc., when the MPU has an access to the data buffer RAM. Thus it is possible to use effectively the area of the RAM and to decrease the number of component chips of a disk controller together with improvement of the flexibility attained at extension of a function.

10. 发明专利

JPH07130105A MAGNETIC MEMORY CONTROLLER 失效
公开(公告)号：JPH07130105A
公开(公告)日：1995-05-19
申请号：JP30236093
申请日：1993-11-08
申请人： HITACHI LTD
发明人： HISADA SHINICHI
IPC分类号： G11B20/14
摘要： PURPOSE:To prevent a reading-out error even at the time of a non-selection state by continuing phase comparison for a specified period via a counter when a read gate signal changes over to the non-selection state. CONSTITUTION:The phases of data Data and a reference signal RefCUX are compared by a frequency phase comparator 5 and VFO1 is controlled according to the results of comparison when the read gate signal RG is selected. The data DI and the signal RefCLK are then synchronized with the clock C1 from the VFO1 and the data are read out in this state. The comparison by the comparator 5 is continued within the specified period by an RG gate period counter 4 and the reading-out error is prevented when the signal RG is changed over to the non-selection. The WSP of a recording format is shortened and the storage capacity is increased. The similar result is obtd. even if the gain of a frequency control loop is made small in place of the continuous comparison.

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