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1. 发明专利

JPH02172071A PHASE LOCKED LOOP CIRCUIT 失效
公开(公告)号：JPH02172071A
公开(公告)日：1990-07-03
申请号：JP32331688
申请日：1988-12-23
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： SAIKI EISAKU , SUZUMURA SHINTARO , KARASAWA TOKUYUKI , KOJIMA SHINICHI , SHIRAISHI KAZUHISA , MINOJIMA SATOSHI
IPC分类号： G11B20/14 , H03L7/08
摘要： PURPOSE:To obtain a readout signal with accurate pulse width without any adjustment by using a delay circuit able to set a dealy with high accuracy, and retarding a VCO signal for a prescribed time with respect to an external input signal. CONSTITUTION:Readout information RD51 is fed to an RD signal generating circuit 1a of a phase comparator 1, an INC (flow-out current of charge pump 2) signal generator 1b and a CK terminal of each DFF of a DEC (drawout current) signal generator 1c, and the leadout signal 57, the INC signal 53 and the DEC signal are raised at the front ridge of the RD51. The delay readout information 58, the DFF 113 and the signal resulting from the signal 58 through delay and polarity inversion are inputted to a 3-input NAND 116, the readout signal is fallen at the front ridge of the signal 58 to obtain the signal 57 with a pulse width of the phase difference between the signals 51 and 58. The circuit 1b falls the INC signal 53 at the front ridge of the delay output 61 and the pulse width is prolonged by that of the signal 57 by a delay tau3. The circuit 1c falls the DEC signal 54 at the trailing edge of the delay output 62 to prolong the pulse width by a delay tau4. Since the relation of tau3=tau4 exists, the pulse width of the signals 57, 53 is set with no adjustment and the width is constant independently of power supply and temperature.

2. 发明专利

JPS56165351A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS56165351A
公开(公告)日：1981-12-18
申请号：JP6895780
申请日：1980-05-26
申请人： HITACHI LTD
发明人： MINOJIMA SATOSHI
IPC分类号： H01L27/082 , H01L21/331 , H01L21/8226 , H01L27/02 , H01L29/73
摘要： PURPOSE:To make voltage between emitters and bases constant by wiring sections between the emitters of inverter type Trs by buried regions and sections between the emitter regions of lateral type Trs by conductors with resistance equal to the buried regions in a device consisting of a plurality of I L elements. CONSTITUTION:Wiring 5 is polysilicon layers or P regions with sheet resistance equal to N buried regions 3 used as injector lines wiring sections between the injectors of I L cells. Wiring 4 is the N buried regions 3 used as ground lines wiring sections between the grounds of the I L cells. Accordig to such wiring, since difference VBE between a ground level and an injector level does not change due to distance and is a fixed value, the speed of switching of the I L does not slow, and an area of a chip can be reduced.

3. 发明专利

JPH07302403A METHOD AND DEVICE FOR MAGNETIC RECORDING 失效
公开(公告)号：JPH07302403A
公开(公告)日：1995-11-14
申请号：JP9604194
申请日：1994-05-10
申请人： HITACHI LTD
发明人： MIYASAKA HIDEKI , NITTA TOSHIHIRO , MINOJIMA SATOSHI
IPC分类号： G11B5/09 , C04B28/18 , G11B20/10 , G11B20/18
摘要： PURPOSE:To surely record desired signal waveforms corresponding one to one to an input code string on a magnetic recording medium without depending on the state of a precoder. CONSTITUTION:This device is provided with a magnetic recording and reproducing channel provided with a recording system consisting of a precoder 1 including delay operators 2 and 3 performing respectively delay operations for one bit period and an adder 4 performing a mod 2 operation, a recording amplifier 6 and a recording head 7 and with a reproducing system consisting of a reproducing head 8, a reproducing amplifier 9, a high frequency band compensating circuit 10, a one-bi t delay circuit 11, a timing reproducing circuit 12, an adding circuit 13 and a three value deciding circuit 14. Then, a reset timing generator 5 generating a rest signal (g) resetting the precoder l is provided in the device and then arbitrary signal waveforms corresponding one to one to the input code string can be generated and recorded on the recording medium without depending on the state of the precoder 1 by resetting the precoder 1 while allowing the reset signal (g) to be genera ted in a desired timing.

4. 发明专利

JPS61105104A Semiconductor circuit 失效
标题翻译：半导体电路
公开(公告)号：JPS61105104A
公开(公告)日：1986-05-23
申请号：JP22572384
申请日：1984-10-29
申请人： Hitachi Ltd
发明人： MINOJIMA SATOSHI
IPC分类号： H03F3/343 , H03F3/34
摘要： PURPOSE: To realize a high accuracy current mirror circuit having a wide dynamic range by allowing a current correction circuit to correct an excess base current due to a low current amplification factor of an output pnp transistor (TR) without provision of an excess circuit to a collector.
CONSTITUTION: The current correction circuit consists of a current mirror circuit comprising a PNP TRO
1 -1 and a pnp TRO
2 -2 and a current mirror circuit those of the Q
2 -2, a pnp TRO
4 -4 whose emitter is connected to a collector of the Q
3 -3 and npn TRsQ
5 -5 and Q
6 -6 copying the base current of the Q
4 -4 and whose output is connected to the base of the Q
2 -2. The same emitter area is used for the Q
2 -2, Q
3 -3 and Q
4 -4 so as to apply the same copy rate and the Q
6 -6 has the emitter area causing 4 times of the current copy rate to that of the Q
5 -5, then the current copy with high accuracy is attained regardless of a low current amplification factor of pnp TRs.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过允许电流校正电路由于输出pnp晶体管（TR）的低电流放大系数而校正过剩的基极电流，从而实现具有宽动态范围的高精度电流镜电路，而不会产生过多的电路集电极。构成：电流校正电路由包括PNP TRO1-1和pnp TRO2-2的电流镜电路和Q2-2的电流镜电路组成，pnp TRO4-4的发射极连接到 Q3-3和npn TRsQ5-5和Q6-6复制Q4-4的基极电流，其输出连接到Q2-2的基极。 Q2-2，Q3-3和Q4-4使用相同的发射极面积，以便施加相同的复制速率，Q6-6的发射极面积使得当前复制速率的4倍于Q5- 如图5所示，无论pnp TR的低电流放大系数如何，都能获得高精度的当前拷贝。

5. 发明专利

JPS60263509A VOLTAGE CONTROLLED OSCILLATOR CIRCUIT 失效
公开(公告)号：JPS60263509A
公开(公告)日：1985-12-27
申请号：JP11948884
申请日：1984-06-11
申请人： HITACHI LTD
发明人： MINOJIMA SATOSHI
IPC分类号： H03K3/282 , H03K5/00 , H03K7/06
摘要： PURPOSE:To raise the oscillated frequency twice or more times without damaging the characteristic of linearity by combining a VCO, voltage control delay circuits, and a logic circuit. CONSTITUTION:The output of a VCO3 passes voltage control delay circuits 8 and 9, and outputs of circuits 8 and 9 are outputted with a phase difference corresponding to the difference of signal transmission delay time between both circuits 8 and 9. If adjusting resistances R2 and R3 are adjusted preliminarily and are so set that the phase difference between both outputs is a half of the pulse width, the two-fold oscillated frequency of the output of the VCO3 is obtained from an exclusive NOR circuit 10. If plural oscillating circuits constituted in this manner are cascaded, the even-fold oscillated frequency of the output of the VCO in the first stage is obtained. Thus, the oscillated frequency is raised twice or more times without damaging the characteristic of linearity.

6. 发明专利

JPS5730405A Semiconductor circuit 失效
标题翻译：半导体电路
公开(公告)号：JPS5730405A
公开(公告)日：1982-02-18
申请号：JP10524380
申请日：1980-07-31
申请人： Hitachi Ltd
发明人： MINOJIMA SATOSHI
IPC分类号： H03F1/26 , H03F1/08 , H03F1/22
CPC分类号： H03F1/083 , H03F1/22
摘要： PURPOSE:To avoid the effect of coolector capacity of a low noise transistor (TR), by connecting a norator having less collector capacitance between the collector and a load circuit of a low noise TR having greater collector capacitance. CONSTITUTION:A low noise TR11 is used as a differential amplifier, a TR16 of low collector capacity is connected as the norator to a load of the TR11, and a load 12 is connected as the norator load. Since the TR16 is connected to the load of the TR11 as the norator, even if the value of a collector capacity 13 of the TR11 is greater, as the decisive element of the cut-off frequency at an output OUT, the values of a capacity 17 of the TR16 and a load resistor 12 are related, allowing to provide a circuit having wide band.
摘要翻译：目的：为了避免低噪声晶体管（TR）的共调谐器容量的影响，通过将具有较小集电极电容的集电极和具有较大集电极电容的低噪声TR的负载电路之间的调谐器电容连接起来。构成：将低噪声TR11用作差分放大器，将低收集器容量的TR16作为转换器连接到TR11的负载，负载12作为绕组负载连接。由于TR16连接到TR11的负载作为调零器，所以即使TR11的集电极容量13的值较大，作为输出OUT的截止频率的决定性要素， TR16中的17和负载电阻12相关，允许提供具有宽带的电路。

7. 发明专利

JP2008026074A Ic test method and ic 审中-公开
标题翻译： IC测试方法和IC
公开(公告)号：JP2008026074A
公开(公告)日：2008-02-07
申请号：JP2006197107
申请日：2006-07-19
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： IBARAKI TAKAYUKI , TAKESHIMA MASANORI , MINOJIMA SATOSHI , YAMASHITA SHINJI , SUZUKI HITOSHI
IPC分类号： G01R31/28
摘要： PROBLEM TO BE SOLVED: To provide a technology which can diagnose especially the AC characteristics of an I/O section in an IC, for which diagnoses/tests have been conventionally impossible and not performed, in order to reduce percent defective in IC products constituting a storage device, thereby allowing to detect defective components and improve quality.
SOLUTION: In an LSI 100, the I/O section 110, which is an object to be diagnosed/tested, is provided outside a local clock section 101. In the configuration where an input buffer section 111 and an output buffer section 121 of interest are sandwiched by FFs 133, 143 of testing common circuit sections 131, 141 and FFs 103, 104 of the local clock section 101, diagnoses/tests are performed using an RAGR 161 and an MISR 162.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供可以诊断IC中的I / O部分的AC特性的技术，其通常不可能进行诊断/测试，并且不进行诊断/测试，以便减少IC中的缺陷百分比产品构成存储装置，从而允许检测有缺陷的部件并提高质量。解决方案：在LSI100中，作为被诊断/测试对象的I / O部分110被设置在本地时钟部分101的外部。在输入缓冲器部分111和输出缓冲器部分感兴趣的121被夹在本地时钟部分101的测试公用电路部分131,141和FF103,104的FF 133,133之间，使用RAGR 161和MISR 162执行诊断/测试。 C）2008，JPO＆INPIT

8. 发明专利

JPH0896312A INFORMATION RECORDING AND REPRODUCING DEVICE AND SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPH0896312A
公开(公告)日：1996-04-12
申请号：JP7500995
申请日：1995-03-31
申请人： HITACHI LTD
发明人： SATO NAOKI , MITA SEIICHI , MIYAZAWA SHOICHI , TAKASHI TERUMI , HORI YOSUKE , WATABE YOSHIHISA , HIRANO AKIHIKO , MINOJIMA SATOSHI , MIYASAKA HIDEKI , NITTA TOSHIHIRO , HIRAI TOMOAKI , SHIMOKAWA RYUSHI , SHIDA KOJI , OUCHI YASUHIDE
IPC分类号： G11B5/035 , G11B5/09 , G11B20/10
摘要： PURPOSE: To easily optimize various parameters in a short time by applying a coefft. correcting circuit for a prescribed equalization circuit and an error detecting circuit, etc., to a signal processing circuit adaptable to high speed transfer or a magnetic recording and reproducing device. CONSTITUTION: An HDA 1 is equipped with a reproducing head 8 using a magneto-resistance effect element, a thin film recording head 9, a recording and reproducing preamplifier 11 and a magnetic disk 10, etc. At the time of recording information, a recording current to be inverted in response to information from a WSPC 2 is supplied via an R/WIC 11 to an IND head 9, and is recorded as magnetizing information on the disk 10 rotating at a fixed revolving speed. At the time of reproducing, the feeble magnetizing information detected by the MR head 8 is amplified via the R/WIC 11, and is outputted to an RSPC 3. A recording current for the IND head and a sense current for the MR head are controlled in size by the WSPC 2 and the RSPC 3, while rotating operation of the disk 10 and positioning operation of the IND head 9 and the MR head 8 on the disk 10 are controlled by an SRVC 5.

9. 发明专利

JPH06195402A OPTIMAL DESIGN SUPPORTING SYSTEM FOR PRODUCT DEVELOPMENT 失效
公开(公告)号：JPH06195402A
公开(公告)日：1994-07-15
申请号：JP26647193
申请日：1993-10-25
申请人： HITACHI LTD
发明人： KOJIMA TOSAKU , OHASHI TOSHIJIRO , HAYAKAWA MITSUHARU , NISHIDA HIROSHI , TEZUKA YOJIRO , MORI TERUO , MINOJIMA SATOSHI , IKEDA MASAAKI , ARIMOTO SHIYOUJI
IPC分类号： G05B19/418 , B65G61/00 , G06F17/50 , G06Q50/00 , G06Q50/04 , G06F15/60 , G06F15/21
摘要： PURPOSE:To drastically reduce development manhour by executing optimization by simultaneously evaluating the improvement of the performance of a product, a low cost, the improvement of a quality and a product developing period. CONSTITUTION:Evaluation information based on information concerning the object product of CAD/CAM/CAT processors is generated by a design evaluation information generation part interface 31 and generated evaluation information is inputted to a life cycle cost simulator 50. The simulator 50 executes simulation by associating the quality of the product and the cost. A user interface 60 inputs a parameter, etc., by interactive input to the simulation. Besides, the user interface 60 refers to and changes the knowledge base of a rule base expert system 90 consisting of an object directivity data base. A design rule check 75 executes rule-check based on the expert system 90, design information 80 of the object product and evaluation information.

10. 发明专利

JPS60175444A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60175444A
公开(公告)日：1985-09-09
申请号：JP3021684
申请日：1984-02-22
申请人： HITACHI LTD
发明人： MINOJIMA SATOSHI , HASHIMOTO KAZUYA
IPC分类号： H01L25/065 , H01L25/07 , H01L25/16 , H01L25/18 , H01L27/00
摘要： PURPOSE:To integrate a low noise amplifier circuit by connecting a small scale gallium arsenide semiconductor and a large scale silicon semiconductor via thermal melting through low melting point conductive material. CONSTITUTION:In a semiconductor device, a gallium arsenide substrate 2 in which a connecting lead terminal 7 on the substrate 2 and a connecting lead terminal 8 on a silicon substrate 1 are deposited with solder ball 3 is connected with the terminals 7, 8 by thermally melted solder by passing the thermal step of approx. 300 deg.C by superposing the substrates 2, 1 oppositely at upper and lower sides. When low noise gallium arsenide transistor is used for an input transistor 6, the same circuit noise amount as the case that all are formed of gallium arsenide semiconductors even if the circuit except it is composed of silicon semiconductor.

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