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1. 发明专利

JP2010165179A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010165179A
公开(公告)日：2010-07-29
申请号：JP2009006947
申请日：2009-01-15
申请人： Hiroshima Univ , Renesas Technology Corp , 国立大学法人広島大学 , 株式会社ルネサステクノロジ
发明人： ISHIZAKI MASAKATSU , KUMAKI TAKESHI , TAGAMI SEIJI , IMAI YUTA , KOIDE TETSUSHI , MATTHEW HANSJUERGEN , GYOTEN TAKAYUKI , NODA HIDEYUKI , OKUNO YOSHIHIRO , ARIMOTO KAZUTAMI
IPC分类号： G06F7/533
CPC分类号： G06F7/5235 , G06F7/5324 , G06F7/5338
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of speeding up an arithmetic operation and enhancing parallelism by being downsized. SOLUTION: The semiconductor device 201 includes: decoders DEC1 and DEC2 for receiving first multiplier data of 3 bits indicating a multiplier to output a shift flag, an inversion flag, and an operation flag in accordance with Booth's algorithm; and first partial product calculation units 31 to 38 for receiving first multiplicand data of 2 bits indicating a multiplicand, a shift flag, an inversion flag, and an operation flag to select one of the higher order bit and lower order bit of the first multiplicand data based on the shift flag, and for inverting or non-inverting the selected bit based on the inversion flag, and for selecting one of the inverted or non-inverted data and the data of a predetermined logic level based on the operation flag, and for outputting the selected data as partial product data indicating the partial product of the first multiplier data and the first multiplicand data. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够加速算术运算并通过小型化来提高并行性的半导体器件。解决方案：半导体器件201包括：解码器DEC1和DEC2，用于根据布斯算法接收指示乘法器的3位的第一乘法器数据，以输出移位标志，反转标志和操作标志; 以及第一部分乘积计算单元31至38，用于接收指示被乘数的2位的第一被乘数数据，移位标志，反转标志和操作标志，以选择第一被乘数数据的高位位和低位位之一基于所述移位标志，以及用于基于所述反转标志反相或非反相所选择的位，并且用于基于所述操作标志来选择所述反相或非反相数据之一以及预定逻辑电平的数据，并且为了将所选择的数据作为表示第一乘法器数据和第一被乘数数据的部分乘积的部分乘积数据输出。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2008102680A Processor and table conversion method using the same 有权
标题翻译：使用其的处理器和表转换方法
公开(公告)号：JP2008102680A
公开(公告)日：2008-05-01
申请号：JP2006283803
申请日：2006-10-18
申请人： Hiroshima Univ , Renesas Technology Corp , 国立大学法人広島大学 , 株式会社ルネサステクノロジ
发明人： GYOTEN TAKAYUKI , DOSAKA KATSUMI , NODA HIDEYUKI , ARIMOTO KAZUTAMI , KURODA YASUTO , KUMAKI TAKESHI , KOIDE TETSUSHI , MATTHEW HANSJUERGEN , ISHIZAKI MASAKATSU
IPC分类号： G06F15/80 , G06T1/20
摘要： PROBLEM TO BE SOLVED: To provide a processor whose high speed operation is possible by using a bit serial type SIMD machine.
SOLUTION: An orthogonal SRAM0(21) and an orthogonal SRAM1(22) horizontally write data input from the outside, and vertically read the written data, and output the data to a bit serial type SIMD machine 1. Also, the orthogonal SRAM0(21) and orthogonal SRAM1(22) vertically write data to be output from the bit serial type SIMD machine 1, and horizontally read the written data, and output the data to the outside. Therefore, it is possible for the bit serial type SIMD machine 1 to quickly perform an arithmetic operation.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种使用位串行SIMD机可以进行高速运行的处理器。解决方案：正交SRAM0（21）和正交SRAM1（22）水平写入从外部输入的数据，并垂直读取写入的数据，并将数据输出到位串行SIMD机1.而且，正交 SRAM0（21）和正交SRAM1（22）垂直写入要从位串行SIMD机1输出的数据，并水平读取写入的数据，并将数据输出到外部。因此，位串行型SIMD机1可以快速执行算术运算。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2013101729A Content addressable memory 有权
标题翻译：内容可寻址内存
公开(公告)号：JP2013101729A
公开(公告)日：2013-05-23
申请号：JP2011243733
申请日：2011-11-07
申请人： Hiroshima Univ , 国立大学法人広島大学
发明人： KOIDE TETSUSHI , MATTHEW HANSJUERGEN , YASUDA MASAHIRO , SASAKI SEIRYU
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： PROBLEM TO BE SOLVED: To provide a content addressable memory in which false retrieval can be suppressed.SOLUTION: A content addressable memory comprises R pieces of distance/time conversion circuits DTto DT. Each of the R pieces of distance/time conversion circuits DTto DTincludes a NAND circuit 40 and N-bit stages 41-4k. Each of the N-bit stages 41-4k oscillates an oscillation signal by delaying a signal from the NAND circuit 40 with a longer delay time as a distance between reference data and retrieval data increases, and oscillates the oscillation signal by delaying the signal from the NAND circuit 40 with a shorter delay time as the distance between the reference data and the retrieval data decreases. Among R pieces of oscillation signals outputted from the distance/time conversion circuits DTto DT, an oscillation signal which is changed on the earliest stage is detected as an oscillation signal of a Winner row.
摘要翻译：要解决的问题：提供可以抑制错误检索的内容可寻址存储器。解决方案：内容可寻址存储器包括R个距离/时间转换电路DT 1 到DT R 。距离/时间转换电路DT 1 到DT R 中的每一个包括NAND电路40和N位级 41-4k。 N位级41-4k中的每一个通过在参考数据和检索数据之间的距离增加时以较长的延迟时间延迟来自NAND电路40的信号来振荡振荡信号，并且通过延迟来自 NAND电路40随着参考数据和检索数据之间的距离减小而具有较短的延迟时间。在从距离/时间转换电路DT 1 输出的R个振荡信号中，在DT R 中，振荡信号被改变在最早阶段被检测为优胜者行的振荡信号。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2005190429A Reference data recognition/learning method and pattern recognition system 审中-公开
标题翻译：参考数据识别/学习方法和模式识别系统
公开(公告)号：JP2005190429A
公开(公告)日：2005-07-14
申请号：JP2003434596
申请日：2003-12-26
申请人： Hiroshima Univ , 国立大学法人広島大学
发明人： MATTHAEUS HANSJUERGEN , KOIDE TETSUSHI , MIZOGAMI MASAHIRO
IPC分类号： G06N3/08 , G06F17/30 , G06K9/00 , G06K9/66 , G06T7/00
CPC分类号： G06K9/66 , G06K9/00986 , Y10S707/99937
摘要： PROBLEM TO BE SOLVED: To provide a reference data recognition/learning method which automatically learns data of high appearance frequencies without requiring teacher data. SOLUTION: In processing (a), reference data being at the shortest distance to input data is detected as a winner. In processing (b), it is discriminated whether the distance between input data and the winner is shorter than a threshold or not. In processing (c), reference data detected as the winner is regarded as coinciding with input data and the rank of reference data is raised in the case that the distance between input data and the winner is shorter than the threshold. In processing (d), reference data detected as the winner is regarded as different from input data and input data is written in an associative memory as new reference data in the case that the distance between input data and the winner is equal to or longer than the threshold. In this case, reference data in higher ranks are stored for a longer period, and reference data in lower ranks are stored for a shorter period, and a rise width of the rank of reference data detected as the winner is properly set, and reference data is registered in a short-period storage or a long-period storage in accordance with a coincidence frequency. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种参考数据识别/学习方法，其自动学习高出现频率的数据，而不需要教师数据。解决方案：在处理（a）中，以与输入数据最短的距离的参考数据被检测为获胜者。在处理（b）中，判别输入数据和胜者之间的距离是否短于阈值。在处理（c）中，作为胜者检测到的参考数据被认为与输入数据一致，并且在输入数据和获胜者之间的距离小于阈值的情况下引起参考数据的等级。在处理（d）中，作为获胜者检测到的参考数据被认为与输入数据不同，并且在输入数据和获胜者之间的距离等于或大于的情况下，输入数据被写入关联存储器中作为新的参考数据门槛。在这种情况下，较高级别的参考数据被存储较长时间段，较低级别的参考数据被存储较短的时间段，并且被正确地设置作为获胜者检测到的参考数据的等级的上升幅度，以及参考数据根据符合频率被记录在短期存储或长周期存储中。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2005092362A Image segmentation apparatus, image segmentation method and image segmentation integrated circuit 有权
标题翻译：图像分割装置，图像分割方法和图像分割集成电路
公开(公告)号：JP2005092362A
公开(公告)日：2005-04-07
申请号：JP2003322163
申请日：2003-09-12
申请人： Hiroshima Univ , 国立大学法人広島大学
发明人： KOIDE TETSUSHI , MATTHAEUS HANSJUERGEN , MORIMOTO TAKASHI , HARADA HIROAKI
IPC分类号： G06T1/00 , G06T1/20 , G06T5/00 , G06T5/30
CPC分类号： G06K9/342 , G06K9/00986 , G06T7/11 , G06T7/20 , G06T2200/28 , G06T2207/10016
摘要： PROBLEM TO BE SOLVED: To achieve real time image segmentation with low power consumption even in a large-scaled image. SOLUTION: In a Boundary Active Only(BAO) Scheme proposed by this invention, only cells which are present in the boundary of region growth are set in an active mode, and the other cells are set in a stand-by mode. The state transition processing of those respective cells is executed in parallel, and when any of three conditions that any of adjacent cells is not ignited, that the cell itself has been already ignited, and that the cell belongs to an existing segmentation area is satisfied, the decision of the state transition to be performed in each clock cycle is not executed under the consideration of the fact that the status transaction is actually operated only when any cell is not present in the boundary of the area growth of the ignited cell with a leader cell as a start point. Thus, it is possible to reduce power consumption by automatically controlling the number of cells to be simultaneously operated and the number of coupled weight registers. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：即使在大尺寸图像中也能实现低功耗的实时图像分割。解决方案：在本发明提出的仅限边界有效（BAO）方案中，仅存在于区域增长边界的单元被设置为活动模式，而其它单元被设置为待机模式。并行执行各个小区的状态转移处理，并且当任何相邻小区未点燃的三个条件中的任一个，小区本身已经被点燃并且小区属于现有分割区域时，在每个时钟周期中执行状态转换的决定不是在仅考虑事实情况下执行的，即只有当任何单元不存在于具有引导者的点燃单元的区域增长的边界中时，实际操作单元格作为起点。因此，可以通过自动控制要同时操作的单元数量和耦合加权寄存器的数量来降低功耗。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2011123679A Feature detection device, program for making computer execute feature detection and computer-readable recording medium recording the same 有权
标题翻译：特征检测装置，用于制作计算机执行特征检测的程序和记录其的计算机可读记录介质
公开(公告)号：JP2011123679A
公开(公告)日：2011-06-23
申请号：JP2009280961
申请日：2009-12-10
申请人： Hiroshima Univ , 国立大学法人広島大学
发明人： KOIDE TETSUSHI , MATTHEW HANS JUERGEN , KUMAKI TAKESHI , IMAI YUTA
IPC分类号： G06T7/00
摘要： PROBLEM TO BE SOLVED: To provide a feature detection device capable of rapidly detecting a feature. SOLUTION: An accumulation module accumulates a cumulative value of the luminance of each pixel included in one row to a row direction in parallel to all rows (step S4). An accordance processing module scans a plurality of scan windows to the row direction in parallel, calculates a light/shade difference of a pixel area based on a shape of a Haar feature, verifies accordance between the calculated light/shade difference of the pixel area and a light/shade difference of the Haar feature, and executes the processing of calculating the cumulative value q k that is a verification result of the accordance to the row direction in parallel. A strong discriminator module compares the cumulative value q k with a threshold T, and executes the processing of deciding that a face of a person is detected to the row direction in parallel when the cumulative value q k not smaller than the threshold T is detected. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供能够快速检测特征的特征检测装置。解决方案：累积模块将行中包含的每个像素的亮度的累积值累加到与所有行并行的行方向（步骤S4）。一致处理模块并行地扫描多个扫描窗口到行方向，基于Haar特征的形状计算像素区域的亮/暗差，验证所计算的像素区域的光/阴差与 Haar特征的亮度/亮度差异，并且执行作为行方向的验证结果并行计算的累积值q SB> k 的处理。强鉴别器模块将累积值q k 与阈值T进行比较，并且当累加值q 时执行决定人的脸部被并行地检测到行方向的处理，检测不到阈值T的k 。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2014041676A Content addressable memory 有权
标题翻译：内容可寻址内存
公开(公告)号：JP2014041676A
公开(公告)日：2014-03-06
申请号：JP2012183975
申请日：2012-08-23
申请人： Hiroshima Univ , 国立大学法人広島大学
发明人： MATTHEW HANSJUERGEN , KOIDE TETSUSHI , SASAKI SEIRYU , AKAZAWA TOMONOBU
IPC分类号： G11C15/04
CPC分类号： G11C15/04 , G11C15/00
摘要： PROBLEM TO BE SOLVED: To provide a content addressable memory which allows accurate and rapid similarity search even when using Manhattan distances.SOLUTION: The content addressable memory includes R distance/clock count conversion circuits DCto DCeach of which includes counter matching detection circuits 31 to 3W. Each of distance signals Dto Drepresents a distance between search data and reference data. The counter matching detection circuit 31 counts the number of clocks for acquisition of a counter value matching the distance signal D, and then the counter matching detection circuit 32 counts the number of clocks for acquisition of a counter value matching the distance signal D. The same operation is performed hereafter, and the counter matching detection circuit 3W counts the number of clocks for acquisition of a counter value matching a distance signal Dafter the counter matching detection circuit 3W-1 counts the number of clocks for acquisition of a counter value matching a distance signal D.
摘要翻译：要解决的问题：提供一种内容可寻址存储器，即使在使用曼哈顿距离时也允许精确和快速的相似性搜索。解决方案：内容可寻址存储器包括R个距离/时钟计数转换电路DCto DCe，其中包括计数器匹配检测电路31至3W 。每个距离信号Dto D表示搜索数据和参考数据之间的距离。计数器匹配检测电路31计数用于获取与距离信号D匹配的计数器值的时钟数，然后计数器匹配检测电路32计数用于获取与距离信号D匹配的计数器值的时钟数。相同计数器匹配检测电路3W计数与计数器匹配检测电路3W-1对应的距离信号D匹配的计数器值的时钟数，计数器的数目用于获取匹配距离的计数器值信号D.

8. 发明专利

JP2009134810A Associative memory and searching system using the same 有权
标题翻译：相关记忆和搜索系统
公开(公告)号：JP2009134810A
公开(公告)日：2009-06-18
申请号：JP2007309856
申请日：2007-11-30
申请人： Hiroshima Univ , 国立大学法人広島大学
发明人： ABEDIN M ANWARUL , KOIDE TETSUSHI , MATTHEW HANSJUERGEN , TANAKA YUKI
IPC分类号： G11C15/04
CPC分类号： G11C11/56 , G11C15/04
摘要： PROBLEM TO BE SOLVED: To provide an associative memory capable of outputting multiple reference data close to search data. SOLUTION: A memory array 10 compares each piece of the multiple reference data with the search data in parallel and generates multiple comparison current signals C 1 to C R representing the result of the comparison. A WLA circuit 20 converts the multiple comparison current signals C 1 to C R into multiple voltages V C1 to V CR . During the first cycle, the WLA circuit 20 detects a lowest voltage among the multiple voltages V C1 to V CR as Winner, and the remaining voltages as Loser. After the second cycle, based on feedback signals FB 1 to FB R , the WLA circuit 20 detects all the voltages other than the voltage detected as Winner during the last preceding cycle, and detects a lowest voltage among the detected voltages as Winner and the remaining detected voltages as Loser. The WLC circuit 20 repeats these operations k times. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够输出接近搜索数据的多个参考数据的关联存储器。存储器阵列10并行地将多个参考数据和搜索数据并行地进行比较，并且生成表示该多个参考数据的多个参考数据的多个比较电流信号C 1 至C R 比较结果。 WLA电路20将多个比较电流信号C 1 转换为C R 为多个电压V SB C1至SB SB >。在第一周期期间，WLA电路20检测作为优胜者的多个电压V SB> C1 至V SB SB的最低电压，剩余电压作为失败者检测。在第二周期之后，WLA电路20基于反馈信号FB 1 到FB R ，检测在最后一个周期内被检测为Winner的电压以外的所有电压，并检测检测到的电压中的最低电压为Winner，剩余检测电压为失败者。 WLC电路20重复这些操作k次。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2006260127A Interconnection network and multiport memory using the same 审中-公开
标题翻译：互连网络和使用相同的多媒体存储器
公开(公告)号：JP2006260127A
公开(公告)日：2006-09-28
申请号：JP2005076253
申请日：2005-03-17
申请人： Hiroshima Industrial Promotion Organization , Hiroshima Univ , 国立大学法人広島大学 , 財団法人ひろしま産業振興機構
发明人： MATTHEW HANS JUERGEN , KOIDE TETSUSHI , HIRONAKA TETSUO , INOUE TOMOHIRO
IPC分类号： G06F12/06
摘要： PROBLEM TO BE SOLVED: To provide an interconnection network that quickly and simply addresses a many-to-many assignment problem, and a multiport memory using the same. SOLUTION: The multiport memory 10 comprises the interconnection network 11 having input ports 12 and output ports 13, and memory blocks 14 each connected to the interconnection network 11 via an output part 18 comprising a plurality of output ports 13. The interconnection network 11 may be EBSF 30. Outputs of the EBSF 30 are not bound to a single port but output independently to the memory blocks 14. The EBSF 30 can thus be used as an interconnection network and an arbitration function. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供快速简单地解决多对多分配问题的互连网络，以及使用该互连网络的多端口存储器。解决方案：多端口存储器10包括具有输入端口12和输出端口13以及各自经由包括多个输出端口13的输出部分18连接到互连网络11的存储器块14的互连网络11.互连网络 11可以是EBSF 30.EBSF 30的输出不限于单个端口，而是独立于存储器块14输出。因此，EBSF 30可以用作互连网络和仲裁功能。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2005209317A Minimum manhattan distance retrieving associative memory device 审中-公开
标题翻译：最小的曼哈顿距离检索相关的存储器件
公开(公告)号：JP2005209317A
公开(公告)日：2005-08-04
申请号：JP2004017429
申请日：2004-01-26
申请人： Hiroshima Univ , 国立大学法人広島大学
发明人： KOIDE TETSUSHI , MATTHAEUS HANSJUERGEN , YANO YUJI
IPC分类号： G11C15/04 , G06T7/00 , G11C15/00
CPC分类号： G11C15/00
摘要： PROBLEM TO BE SOLVED: To provide a minimum manhattan distance retrieving associative memory device which is realized with low power consumption and small area, and at high speed by realizing a manhattan distance calculating circuit with small area.
SOLUTION: A circuit performing calculation of an absolute value of difference for associative memory is realized. This circuit is constituted of two circuits of an addition circuit and a bit inversion circuit and has advantage such that the number of transistors is drastically reduced to approximately 1/3 of conventional one. This absolute value calculating circuit of difference is incorporated in a all parallel type associative memory as a unit comparison circuit UC, and all output of the absolute value calculating circuit of difference of W pieces are inputted to a weight comparing circuit and processed. Thereby, calculation of Manhattan distance of retrieving data and reference data is realized. As the Manhattan distance calculating circuit is realized with small area, an associative memory device also can be realized with low power consumption and small area.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种通过实现具有小面积的曼哈顿距离计算电路实现的，具有低功耗和小面积的高速实现的最小曼哈顿距离检索关联存储器件。解决方案：实现关联存储器的差分绝对值计算的电路。该电路由加法电路和位反转电路的两个电路构成，并且具有这样的优点，使得晶体管的数量大大降低到传统电路的大约1/3。该绝对值计算电路的差异被并入作为单位比较电路UC的全平行型联想存储器中，并且将W个差异的绝对值计算电路的所有输出输入到加权比较电路并进行处理。从而实现了数据和参考数据的曼哈顿距离的计算。由于曼哈顿距离计算电路以小面积实现，所以可以实现低功耗和小面积的关联存储器件。版权所有（C）2005，JPO＆NCIPI

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