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1. 发明专利

JP2008102680A Processor and table conversion method using the same 有权
标题翻译：使用其的处理器和表转换方法
公开(公告)号：JP2008102680A
公开(公告)日：2008-05-01
申请号：JP2006283803
申请日：2006-10-18
申请人： Hiroshima Univ , Renesas Technology Corp , 国立大学法人広島大学 , 株式会社ルネサステクノロジ
发明人： GYOTEN TAKAYUKI , DOSAKA KATSUMI , NODA HIDEYUKI , ARIMOTO KAZUTAMI , KURODA YASUTO , KUMAKI TAKESHI , KOIDE TETSUSHI , MATTHEW HANSJUERGEN , ISHIZAKI MASAKATSU
IPC分类号： G06F15/80 , G06T1/20
摘要： PROBLEM TO BE SOLVED: To provide a processor whose high speed operation is possible by using a bit serial type SIMD machine.
SOLUTION: An orthogonal SRAM0(21) and an orthogonal SRAM1(22) horizontally write data input from the outside, and vertically read the written data, and output the data to a bit serial type SIMD machine 1. Also, the orthogonal SRAM0(21) and orthogonal SRAM1(22) vertically write data to be output from the bit serial type SIMD machine 1, and horizontally read the written data, and output the data to the outside. Therefore, it is possible for the bit serial type SIMD machine 1 to quickly perform an arithmetic operation.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种使用位串行SIMD机可以进行高速运行的处理器。解决方案：正交SRAM0（21）和正交SRAM1（22）水平写入从外部输入的数据，并垂直读取写入的数据，并将数据输出到位串行SIMD机1.而且，正交 SRAM0（21）和正交SRAM1（22）垂直写入要从位串行SIMD机1输出的数据，并水平读取写入的数据，并将数据输出到外部。因此，位串行型SIMD机1可以快速执行算术运算。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2008004249A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2008004249A
公开(公告)日：2008-01-10
申请号：JP2006331968
申请日：2006-12-08
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SHIMANO HIROKI , GYOTEN TAKAYUKI , MORISHITA GEN , DOSAKA KATSUMI
IPC分类号： G11C11/403 , G11C11/401 , G11C11/406 , G11C11/4074
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which power consumption can be further reduced in a standby mode. SOLUTION: When a control signal STBY is input to a power source managing part 40 and asserted, upon receiving it, the power source managing part 40 asserts control signals PD, /PD instructing power reduction. Thereby, supply of the power source for an I/O part 20 is cut off. Also, a control part 30 executes intensive refresh for a memory cell array 15 by assert of a refresh instruction signal/SREF. After refresh operation of a whole memory space is completed, the refresh instruction signal/SREF is negated. After the refresh instruction signal/SREF is negated, a control signal ALIVE is negated, and supply of external power source voltage VDD and ground voltage GND for a power source control circuit 35 is cut off. Before refresh operation, power source supply for the power source control circuit 35 is executed again, and refresh operation is executed. These operations are repeated for each refresh period. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体集成电路器件，其中在待机模式下能够进一步降低功耗。解决方案：当控制信号STBY被输入到电源管理部分40并被断言时，电源管理部分40在接收到电源管理部分40时断言指示功率降低的控制信号PD / PD。因此，I / O部20的电源的供给被切断。此外，控制部30通过刷新指示信号/ SREF的断言对存储单元阵列15进行强制刷新。在整个存储空间的刷新操作完成之后，刷新指令信号/ SREF被否定。在刷新指令信号/ SREF被否定之后，控制信号ALIVE被否定，并且切断用于电源控制电路35的外部电源电压VDD和地电压GND的电源。在刷新操作之前，再次执行电源控制电路35的电源供应，并执行刷新操作。每个刷新周期都会重复这些操作。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2004039135A Semiconductor integrated circuit device 审中-公开
公开(公告)号：JP2004039135A
公开(公告)日：2004-02-05
申请号：JP2002196094
申请日：2002-07-04
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： DOSAKA KATSUMI
IPC分类号： H03K19/096 , G11C7/10 , G11C11/407 , G11C11/4076 , G11C11/408 , G11C11/4097
CPC分类号： G11C7/1072 , G11C11/4076 , G11C11/4082 , G11C11/4097 , G11C2207/2281
摘要： PROBLEM TO BE SOLVED: To generate an internal timing control signal varied at high speed without allowing the pulse width of a pulse signal to be restricted by an internal wiring load. SOLUTION: A plurality of main control signal generating circuits including respectively a plurality of main control signals are provided, these circuits are activated successively, and the prescribed main control signal generating circuit is reset at the time of activation of the main control signal. A local control signal is generated by utilizing the rise edge of main control signals of one side group of these plurality of groups main control signals and a fall edge of main control signals of the other groups. COPYRIGHT: (C)2004,JPO

4. 发明专利

JP2010041460A Solid state imaging apparatus 审中-公开
标题翻译：固态成像装置
公开(公告)号：JP2010041460A
公开(公告)日：2010-02-18
申请号：JP2008202728
申请日：2008-08-06
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： KATO HIROSHI , DOSAKA KATSUMI , MORISHITA GEN
IPC分类号： H04N5/335 , H04N5/374 , H04N5/376 , H04N5/378
CPC分类号： H04N5/3742 , H04N5/378
摘要： PROBLEM TO BE SOLVED: To obtain a solid state imaging apparatus with a data transfer function capable of outputting A/D-converted digital data to the outside at high speed. SOLUTION: Each of data blocks DB ((i) is 0 to 7) comprised of eight stages in a data bus part includes a couple of data lines L1, L2 and an amplifier AM connected to the couple of data lines L1, L2. The amplifier AM amplifies signals of the couple of data lines L1, L2 on a couple of data lines LA1, LA2 for amplification in timing indicated by an amplifier enable signal PAE and an amplifier control signal CSLA and outputs results as block data outputs BDout, BZDout. The data blocks DB each comprised of eight stages are then connected from the first stage to the final state so as to impart the block data outputs BDout, BZDout of the preceding stage to the couple of data lines L1, L2 of the following stage as block data inputs BDin, BZDin. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：获得具有能够高速输出A / D转换的数字数据到外部的数据传送功能的固态成像装置。解决方案：由数据总线部分中的八个级组成的数据块DB（（i）为0至7）中的每一个包括一对数据线L1，L2和与之相连的放大器AM 一对数据线L1，L2。放大器AMi放大在一对数据线LA1，LA2上的一对数据线L1，L2的信号，用于放大器使能信号PAE和放大器控制信号CSLA指示的定时放大，以及输出结果作为块数据输出BDout，BZDout。每个由八个级组成的数据块DB i然后从第一级连接到最终状态，以将前一级的块数据输出BDout，BZDout赋予下列数据线L1，L2 作为块数据输入BDin，BZDin。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2009110616A Content addressable memory device 有权
标题翻译：内容可寻址存储器件
公开(公告)号：JP2009110616A
公开(公告)日：2009-05-21
申请号：JP2007283462
申请日：2007-10-31
申请人： Kanazawa Univ , Renesas Technology Corp , 国立大学法人金沢大学 , 株式会社ルネサステクノロジ
发明人： DOSAKA KATSUMI , ARIMOTO KAZUTAMI , MATSUDA YOSHIO
IPC分类号： G11C15/04 , H01L21/8244 , H01L27/11
CPC分类号： G06F17/30982 , G11C15/04 , Y02D10/45
摘要： PROBLEM TO BE SOLVED: To reduce power consumption and a peak current in a content addressable memory device.
SOLUTION: Before search operations in two TCAM cells of a PCAM cell 1 and an NCAM cell 1, a memory controller 100 connects the match line MLp to a power source and connects the match line MLn to a ground, and then connects the match lines MLp and MLn to each other so as that electric potentials of the match lines are the same as each other.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了减少内容可寻址存储器件中的功耗和峰值电流。解决方案：在PCAM单元1和NCAM单元1的两个TCAM单元中的搜索操作之前，存储器控制器100将匹配线MLp连接到电源，并将匹配线MLn连接到地，然后将使匹配线MLp和MLn彼此匹配，使得匹配线的电位彼此相同。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2007294013A Content reference memory 有权
标题翻译：内容参考存储器
公开(公告)号：JP2007294013A
公开(公告)日：2007-11-08
申请号：JP2006120891
申请日：2006-04-25
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： WATANABE NAOYA , HAYASHI ISAMU , AMANO TERUHIKO , MORISHITA GEN , YOSHINAGA KENJI , AKIYAMA MIHOKO , MIYAZAKI SHINYA , ISHIBASHI MASAKAZU , DOSAKA KATSUMI
IPC分类号： G11C15/04
摘要： PROBLEM TO BE SOLVED: To provide a content reference memory performing a high-speed retrieval operation with low current consumption. SOLUTION: A match amplifier 40 for detecting the potential of a match line ML is provided with a precharge transistor 60 for precharging the match line to a ground voltage level, a pullup current supply/determination circuit 100 for supplying a current whose value is limited to the match line during comparison with retrieved data and generating a signal according to the voltage level of the match line, and a capacitance element for supplying charges to the corresponding match line during the comparison. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供以低电流消耗执行高速检索操作的内容参考存储器。解决方案：用于检测匹配线ML的电位的匹配放大器40设置有用于将匹配线预充电到接地电压电平的预充电晶体管60，用于提供其值的电流的上拉电流供应/确定电路100 在与检索到的数据进行比较期间被限制到匹配线，并且根据匹配线的电压电平产生信号，以及用于在比较期间向对应匹配线提供电荷的电容元件。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2007024865A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007024865A
公开(公告)日：2007-02-01
申请号：JP2006060651
申请日：2006-03-07
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： GYOTEN TAKAYUKI , MORISHITA GEN , DOSAKA KATSUMI
IPC分类号： G01K7/01
CPC分类号： G01K7/01
摘要： PROBLEM TO BE SOLVED: To provide a technology capable of detecting the temperature of a semiconductor device with high accuracy. SOLUTION: A temperature detection circuit 14 for detecting the temperature of the semiconductor device comprises a short-period oscillator 15 for generating a clock signal CLK1 having positive-temperature characteristic related to frequency, a short-period oscillator 16 for generating a clock signal CLK2 having a negative temperature characteristic related to frequency, and a temperature signal generating section 17 for generating temperature signal TEMP that varies according to the temperature of the semiconductor device, based on the clock signals CLK1 and CLK2. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够高精度地检测半导体器件的温度的技术。解决方案：用于检测半导体器件的温度的温度检测电路14包括用于产生具有与频率相关的正温特性的时钟信号CLK1的短周期振荡器15，用于产生时钟的短周期振荡器16 信号CLK2具有与频率相关的负温度特性，以及温度信号发生部17，用于根据时钟信号CLK1和CLK2产生根据半导体器件的温度而变化的温度信号TEMP。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2006164183A Semiconductor signal processing device 审中-公开
标题翻译：半导体信号处理装置
公开(公告)号：JP2006164183A
公开(公告)日：2006-06-22
申请号：JP2004358719
申请日：2004-12-10
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： NODA HIDEYUKI , ARIMOTO KAZUTAMI , DOSAKA KATSUMI , SAITO KAZUNORI
IPC分类号： G06F15/80
CPC分类号： G06F7/785 , G11C5/025 , G11C7/1006 , G11C7/18 , G11C8/16 , G11C11/419 , G11C2207/104
摘要： PROBLEM TO BE SOLVED: To increase data transfer efficiency without impairing arithmetic parallelism in a signal processing device for parallel arithmetic processing.
SOLUTION: An orthogonal memory 80 for converting an array of system bus data (DTV) and arithmetic data (DTH) is disposed between a system bus interface and a memory cell mat for storing the arithmetic data. The orthogonal memory comprises dual port memory cells (MCS), and changes the data (DTV) transferred in a bit-parallel and word-serial mode to the word-parallel and bit-serial data (DTH).
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提高数据传输效率而不损害用于并行算术处理的信号处理装置中的算术并行性。解决方案：用于转换系统总线数据（DTV）和算术数据（DTH）的阵列的正交存储器80设置在用于存储算术数据的系统总线接口和存储单元垫之间。正交存储器包括双端口存储器单元（MCS），并且将以比特并行和字串行模式传送的数据（DTV）改变为字 - 并行和位串行数据（DTH）。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2007317342A Content addressable memory 审中-公开
标题翻译：内容可寻址内存
公开(公告)号：JP2007317342A
公开(公告)日：2007-12-06
申请号：JP2006308145
申请日：2006-11-14
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： WATANABE NAOYA , HAYASHI ISAMU , AMANO TERUHIKO , MORISHITA GEN , YOSHINAGA KENJI , AKIYAMA MIHOKO , DOSAKA KATSUMI
IPC分类号： G11C15/04
摘要： PROBLEM TO BE SOLVED: To reduce power consumption during a search cycle of a content addressable memory and to increase the speed of a search operation. SOLUTION: An entry (ERY) including multiple bits of unit cells (UC) each storing data bit is coupled to a match line (ML). The match line is supplied with a charging current (Ip) having a restricted current value smaller than a match line current flowing in a one-bit miss state, but larger than a match line current flowing in an all-bit match state. A precharge voltage level of the match line is restricted to a voltage level (VML) of half a power supply voltage (VDD) or smaller. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了减少内容可寻址存储器的搜索周期期间的功耗，并提高搜索操作的速度。解决方案：包括存储数据位的单位单元（UC）的多位的条目（ERY）被耦合到匹配线（ML）。该匹配线具有充电电流（Ip），该充电电流（Ip）的受限电流值小于在一比特异常状态中流动的匹配线电流，但大于在全位匹配状态下流动的匹配线电流。匹配线的预充电电压电平被限制在一半电源电压（VDD）或更小的电压电平（VML）。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2006092676A Arithmetic circuit using associative memory 审中-公开
标题翻译：使用相关记忆的算术电路
公开(公告)号：JP2006092676A
公开(公告)日：2006-04-06
申请号：JP2004278247
申请日：2004-09-24
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： NODA HIDEYUKI , DOSAKA KATSUMI , ARIMOTO KAZUTAMI
IPC分类号： G11C15/04 , G06F17/30
摘要： PROBLEM TO BE SOLVED: To make it possible to perform high-speed operation and simply perform arithmetic operation of bits between word storage parts at distant positions in the columnar direction. SOLUTION: Data for operation are stored in a CAM cell array 1. When saving in a match line tag register 3 an output of a match line amplifier 2 for detecting a searching result (tag information) outputted to a match line by searching operation, the tag information is immediately transmitted to a word line tag register 4. Then, the tag information taken out from the word line tag register 4 is given to a word line driver 5, and a word line corresponding to the CAM array 1 is activated to perform writing. With this constitution, after a first searching operation, for example, it becomes possible to perform searching operation in one word storage part and writing operation in another word storage part in parallel continuously. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了使得可以执行高速操作并且简单地在柱状方向上的远处位置的字存储部分之间进行位的算术运算。
解决方案：操作数据存储在CAM单元阵列1中。当在匹配线标签寄存器3中保存匹配线路放大器2的输出时，用于检测通过搜索输出到匹配线的搜索结果（标签信息）操作时，将标签信息立即发送到字线标签寄存器4.然后，将从字线标签寄存器4中取出的标签信息提供给字线驱动器5，并且与CAM阵列1对应的字线为激活执行写作。利用这种结构，例如，在第一搜索操作之后，可以在一个字存储部分中执行搜索操作并且连续地并行地并行地写入另一个字存储部分中的操作。版权所有（C）2006，JPO＆NCIPI

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