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1. 发明专利

JP2011123679A Feature detection device, program for making computer execute feature detection and computer-readable recording medium recording the same 有权
标题翻译：特征检测装置，用于制作计算机执行特征检测的程序和记录其的计算机可读记录介质
公开(公告)号：JP2011123679A
公开(公告)日：2011-06-23
申请号：JP2009280961
申请日：2009-12-10
申请人： Hiroshima Univ , 国立大学法人広島大学
发明人： KOIDE TETSUSHI , MATTHEW HANS JUERGEN , KUMAKI TAKESHI , IMAI YUTA
IPC分类号： G06T7/00
摘要： PROBLEM TO BE SOLVED: To provide a feature detection device capable of rapidly detecting a feature. SOLUTION: An accumulation module accumulates a cumulative value of the luminance of each pixel included in one row to a row direction in parallel to all rows (step S4). An accordance processing module scans a plurality of scan windows to the row direction in parallel, calculates a light/shade difference of a pixel area based on a shape of a Haar feature, verifies accordance between the calculated light/shade difference of the pixel area and a light/shade difference of the Haar feature, and executes the processing of calculating the cumulative value q k that is a verification result of the accordance to the row direction in parallel. A strong discriminator module compares the cumulative value q k with a threshold T, and executes the processing of deciding that a face of a person is detected to the row direction in parallel when the cumulative value q k not smaller than the threshold T is detected. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供能够快速检测特征的特征检测装置。解决方案：累积模块将行中包含的每个像素的亮度的累积值累加到与所有行并行的行方向（步骤S4）。一致处理模块并行地扫描多个扫描窗口到行方向，基于Haar特征的形状计算像素区域的亮/暗差，验证所计算的像素区域的光/阴差与 Haar特征的亮度/亮度差异，并且执行作为行方向的验证结果并行计算的累积值q SB> k 的处理。强鉴别器模块将累积值q k 与阈值T进行比较，并且当累加值q 时执行决定人的脸部被并行地检测到行方向的处理，检测不到阈值T的k 。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2010165179A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010165179A
公开(公告)日：2010-07-29
申请号：JP2009006947
申请日：2009-01-15
申请人： Hiroshima Univ , Renesas Technology Corp , 国立大学法人広島大学 , 株式会社ルネサステクノロジ
发明人： ISHIZAKI MASAKATSU , KUMAKI TAKESHI , TAGAMI SEIJI , IMAI YUTA , KOIDE TETSUSHI , MATTHEW HANSJUERGEN , GYOTEN TAKAYUKI , NODA HIDEYUKI , OKUNO YOSHIHIRO , ARIMOTO KAZUTAMI
IPC分类号： G06F7/533
CPC分类号： G06F7/5235 , G06F7/5324 , G06F7/5338
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of speeding up an arithmetic operation and enhancing parallelism by being downsized. SOLUTION: The semiconductor device 201 includes: decoders DEC1 and DEC2 for receiving first multiplier data of 3 bits indicating a multiplier to output a shift flag, an inversion flag, and an operation flag in accordance with Booth's algorithm; and first partial product calculation units 31 to 38 for receiving first multiplicand data of 2 bits indicating a multiplicand, a shift flag, an inversion flag, and an operation flag to select one of the higher order bit and lower order bit of the first multiplicand data based on the shift flag, and for inverting or non-inverting the selected bit based on the inversion flag, and for selecting one of the inverted or non-inverted data and the data of a predetermined logic level based on the operation flag, and for outputting the selected data as partial product data indicating the partial product of the first multiplier data and the first multiplicand data. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够加速算术运算并通过小型化来提高并行性的半导体器件。解决方案：半导体器件201包括：解码器DEC1和DEC2，用于根据布斯算法接收指示乘法器的3位的第一乘法器数据，以输出移位标志，反转标志和操作标志; 以及第一部分乘积计算单元31至38，用于接收指示被乘数的2位的第一被乘数数据，移位标志，反转标志和操作标志，以选择第一被乘数数据的高位位和低位位之一基于所述移位标志，以及用于基于所述反转标志反相或非反相所选择的位，并且用于基于所述操作标志来选择所述反相或非反相数据之一以及预定逻辑电平的数据，并且为了将所选择的数据作为表示第一乘法器数据和第一被乘数数据的部分乘积的部分乘积数据输出。版权所有（C）2010，JPO＆INPIT

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