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1. 发明专利

JPH06334147A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH06334147A
公开(公告)日：1994-12-02
申请号：JP11813093
申请日：1993-05-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YOSHIDA MASAHIRO
IPC分类号： H01L27/10 , H01L27/105 , H01L27/108 , H01L29/784
摘要： PURPOSE:To make a memory cell region and a peripheral-circuit formation region flat while the high operating characteristic of a memory cell for a high- integration and large-capacity DRAM is being maintained. CONSTITUTION:The main face of a substrate 1 constituting a semiconductor chip is divided into a first element formation region to a fourth element formation region S1 to S4. The first and third element formation regions S1, S3 out of them are used as formation regions for ordinary planar transistors, a tall element which constitutes a memory cell array 11 is formed in the region S1, and an element which constitutes a peripheral circuit 13 such as a control circuit, a clock generation circuit or the like is formed in the region S3. SOI structures are formed respectively of silicon oxide films 2B, 2D and silicon thin films 3B, 3D in the second and fourth element formation regions S2, S4, an element which constitutes peripheral circuits (a driver, a sense amplifier, a decoder and the like) which is of a simple MOS structure and whose height is low is formed in the region S2, and an element which constitutes a substrate- bias generation circuit generating a substrate-bias voltage is formed in the region S4.

2. 发明专利

JPH06148283A MEMORY TESTER 失效
公开(公告)号：JPH06148283A
公开(公告)日：1994-05-27
申请号：JP29405992
申请日：1992-11-02
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YOSHIDA MASAHIRO , KITAME TETSUYA
IPC分类号： G01R31/3183 , G01R31/28 , H01L21/66
摘要： PURPOSE:To set a register while looking a screen by visually displaying the address scanning range of an indicated memory evaluation pattern and to dispense with the correction of a program at each time of alteration. CONSTITUTION:The address scanning range necessary for a display screen 130 is indicated and a window control part 90 develops a screen address on a chip address. The screen address is converted to the register of a pattern program by an inverse address scrambler 80 to be stored. Further, a main program is started to compile the pattern program and a pattern generator 60 generates the test pattern to a device DUT 40 to be measured. Logical data and timing are synthesized to form a test waveform to measure the DUT 40. The generated address of the generator 60 is converted to the address matched with the cell arrangement in a memory to be measured and this address is converted to a display screen address by the window control part 90 and the fail bit map of the memory is displayed to evaluate the DUT 40.

3. 发明专利

JPH04182998A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND DEFECT RELIEVING METHOD THEREOF 失效
公开(公告)号：JPH04182998A
公开(公告)日：1992-06-30
申请号：JP31149890
申请日：1990-11-19
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TANBA AKIHIRO , AKIYAMA NOBORU , KOBAYASHI YUTAKA , YOKOYAMA YUJI , MIYAZAWA KAZUYUKI , YOSHIDA MASAHIRO , MIWA HITOSHI
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04
摘要： PURPOSE:To improve an operating speed without increasing electric power consumption by providing a means for disconnecting a main memory region and an output line. CONSTITUTION:This device has the means 7 for disconnecting the main memory 1 and a common data line which is the output line. The output of an address comparator circuit 11 is inputted to a switch, i.e., the means 7 and a redundancy word drive 2. The address comparator circuit 11 is so programmed that the switch 7 is on and the redundancy word drive 15 is off at the time of non-relief and hat the switch 7 is off and the redundancy word drive 15 is on at the time of relief. The data of the ordinary line and redundancy line are outputted according to the relief and the non-relief without adding the signal for an inhibit operation to an ordinary line decoding circuit (X decoder 104), namely, without inhibiting the rising operation of the line where a defect exists. The high-speed defect relief is executed with the low electric power consumption in this way.

4. 发明专利

JPH09246731A WIRING SUBSTRATE, MANUFACTURE THEREOF AND WIRING SUBSTRATE TESTING METHOD 失效
公开(公告)号：JPH09246731A
公开(公告)日：1997-09-19
申请号：JP4939096
申请日：1996-03-07
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TANABE SHINICHI , HORIUCHI MITSUAKI , MITARAI KAZUKO , KEIKOIN TOSHIAKI , YOSHIDA MASAHIRO
IPC分类号： H05K3/46 , H01L23/522 , H01L23/538
摘要： PROBLEM TO BE SOLVED: To conduct a test a short period of time in a highly reliable manner by a method wherein a dummy wiring, which is formed by the same process of manufacture of the specific wiring of a multilayer wiring. SOLUTION: On an MCM substrate having dummy wirings 7a, 11b and 11c formed by the same process in which wirings 7 and 11, which are specific wirings of multilayer wiring consisting of wirings 3, 7 and 11, a dummy wiring 19 for testing is formed. A test is conducted for judgment whether the MCM substrate is defective or not using said dummy wiring 19 for testing, and then, the dummy wiring 19 is removed from the MCM substrate. Consequently, as the number of pads, where a probe is put on when testing, can be reduced, a simple test can be conducted at high speed in a highly reliable manner.

5. 发明专利

JPS63239678A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS63239678A
公开(公告)日：1988-10-05
申请号：JP7150887
申请日：1987-03-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MIYAKE JUN , KAWAGUCHI HITOSHI , YAMAGUCHI YASUNORI , NAGASHIMA YASUSHI , YOSHIDA MASAHIRO , YUGAWA YOSUKE , SAEKI TETSUYA , OKADA TERUTAKA , MORINO MAKOTO
IPC分类号： G11C11/401 , G11C11/34
摘要： PURPOSE:To execute a data transfer cycle at an optional timing and to increase a data transfer rate of a system by providing a dual port memory with two registers and using these registers alternately in accordance with a prescribed control procedure. CONSTITUTION:The titled device is provided with two data registers DRA1, DRB1 whose respective bits correspond to plural complementary data lines D0, D0-Dn, Dn constituting a memory array M-ARY1. During the serial I/O operation of memory data through one data register DRA1, the memory data can be transferred in parallel through the other data register DRB1 at a comparatively optional timing. Consequently, the serial I/O operation can be continuously repeated at a comparatively rapid data transfer rate and a processor or the like arranged on the outside of the dual port memory can be simplified.

6. 发明专利

JPS63142591A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS63142591A
公开(公告)日：1988-06-14
申请号：JP28885486
申请日：1986-12-05
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MURANAKA MASAYA , YOSHIDA MASAHIRO , KUBONO SHIYOUJI
IPC分类号： G11C11/401 , G11C11/34
摘要： PURPOSE:To attain simplified picture system and low cost by providing a row address generating circuit in a dual port memory thereby having only to supply a serial clock signal externally. CONSTITUTION:A final row address signal supplied externally via a row address buffer RADB is inputted to an address detection circuit RAD via a row address register RAR of a row address generating circuit RAG. Moreover, a row address counter RAC supplies a data transfer row address signal advanced at each data transfer cycle to an address multiplexer AMX and supplies it to the circuit RAD. The circuit RAD compares signals from the counter RAC and the register RAR and when they are coincident, a final address signal syn is sent to a timing control circuit TC via an AND gate circuit AG. Thus, the word line within the designated range is designated sequentially to continue the input/output operation thereby attaining simplicity and low cost.

7. 发明专利

JPS6379296A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS6379296A
公开(公告)日：1988-04-09
申请号：JP22357286
申请日：1986-09-24
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： MURANAKA MASAYA , YOSHIDA MASAHIRO
IPC分类号： G11C11/401 , G11C11/34
摘要： PURPOSE:To attain multi-functioned device without extension of external terminals by applying prescribed combination to control signals supplied externally and executing one mode of a semiconductor storage device depending on its start cycle and plural succeeding start cycles. CONSTITUTION:It is decided that a control signal supplied externally is a dummy cycle being prescribed combination of signals and the succeeding input signal is inputted as a signal having a different meaning from a normal cycle. In this case, the control signal for dummy cycle consists of a law address strobe signal RAS a column address strobe signal CAS and a write enable signal WE, a decision circuit uses the signals CAS, WE being at a low level before the signal RAS goes to a low level to identify the dummy cycle. Then the prescribed function code is inputted/outputted succeedingly. Thus, the dual port memory is provided with a function control circuit, a logic arithmetic circuit, a decoder and a selector.

8. 发明专利

JPS63266487A READ ONLY MEMORY 失效
公开(公告)号：JPS63266487A
公开(公告)日：1988-11-02
申请号：JP9986087
申请日：1987-04-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YOSHIDA MASAHIRO , SAKAI KIKUO
IPC分类号： G11C17/00 , G09G1/00 , G09G5/22

9. 发明专利

JPH02246087A SEMICONDUCTOR STORAGE DEVICE, REDUNDANT SYSTEM THEREOF, AND LAYOUT SYSTEM 失效
公开(公告)号：JPH02246087A
公开(公告)日：1990-10-01
申请号：JP6584389
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO KATSUYUKI , MATSUMOTO YOSHINORI , OKUMA YOSHIYUKI , OGATA SHINKO , YOSHIDA MASAHIRO
IPC分类号： G11C29/00 , G11C7/10 , G11C7/18 , G11C8/10 , G11C11/401 , G11C29/04
摘要： PURPOSE:To reduce the load of a serial input/output line in a multiport memory, and to realize large storage capacity and a high-speed operation by dividing the serial input/output line at a mid point, and providing input/output circuits at both edges. CONSTITUTION:A timing generating circuit TG receives respective types of control signals supplied from an external terminal, decides an operating mode, and generates the operational timing signal of an internal circuit according to the decision. Four memory mats MAT0 to MAT3 divided into two to the right and left around the timing generating circuit TG are divided into upper and lower parts so that the serial input/output line may be divided into equal two parts at the mid point. By such division, the length of the input/output line extended in the longitudinal direction is reduced by half. According to the reduction, the parasitic capacity of the input/output line can be reduced, and the transfer speed of the serially inputted/outputted data can be increased. Thus the large storage capacity and high speed operation can be realized.

10. 发明专利

JPS62121997A DYNAMIC RAM 失效
公开(公告)号：JPS62121997A
公开(公告)日：1987-06-03
申请号：JP26122985
申请日：1985-11-22
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： KAZUUJI KAZUO , YOSHIDA MASAHIRO , KITAME TETSUYA , SAKAI KIKUO , KUBONO SHIYOUJI
IPC分类号： G11C11/401 , G11C11/34 , G11C11/409
摘要： PURPOSE:To quickly clear stored information by making a sense amplifier operable after a write signal is transmitted to plural data lines simultaneously selected. CONSTITUTION:Transistors Q3, Q4-Q5 and Q6 are controlled through a column address buffer C-ADB corresponding to an address and through a column decoder C-DCR, and plural pairs of data lines DL and their inversion DL are selected. Then a write signal from a data input terminal Din is transmitted to the selected data line DL and its inversion DL, and transistors Q1 and Q2 mutually connected to the sense amplifier SA are controlled. Then the sense amplifier SA is made operable, and data is speedily written in plural dynamic RAM cells. If the buffer C-ADB, etc., are controlled to divide the group made of pairs of data lines into blocks and any of them are selected, stored information can be cleared at every block, and clearing of stored information can be made at a high speed.

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