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1. 发明专利

JPH04168692A NONINVERTED BUFFER AND SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH04168692A
公开(公告)日：1992-06-16
申请号：JP29372790
申请日：1990-11-01
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YOKOYAMA YUJI , MIYAZAWA KAZUYUKI , MIWA HITOSHI , WADA SHOJI
IPC分类号： G11C11/409 , G11C7/10 , G11C8/06 , G11C11/417 , H03K19/013 , H03K19/0175 , H03K19/0944
摘要： PURPOSE:To make the operating speed of a noninverted buffer device faster by reducing the total number of the logical stages of the buffer device by integrating the plurality of logical stages of input buffer circuits constituting the buffer device. CONSTITUTION:An n- and p-type MOS transistors Q32 and Q31 are connected in parallel with each other between the base and collector of a bipolar transistor Tr31 and turning on/off of the transistors Q32 and Q31 are respectively controlled by means of the inverted and noninverted signals of input digital signals. The base current of the transistor Tr31 is supplied mainly from the transistor Q31 when the voltage across the gate and source of the transistor Tr31 is high and from the transistor Q32 when the voltage is low. Accordingly, the transistor Tr31 can always make a sufficient amount of collector current to flow, since a sufficient amount of the base current is always supplied to the transistor Tr31. Therefore, a noninverted buffer device which has one logical stage and a high operating speed can be obtained.

2. 发明专利

JPH04182998A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND DEFECT RELIEVING METHOD THEREOF 失效
公开(公告)号：JPH04182998A
公开(公告)日：1992-06-30
申请号：JP31149890
申请日：1990-11-19
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TANBA AKIHIRO , AKIYAMA NOBORU , KOBAYASHI YUTAKA , YOKOYAMA YUJI , MIYAZAWA KAZUYUKI , YOSHIDA MASAHIRO , MIWA HITOSHI
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04
摘要： PURPOSE:To improve an operating speed without increasing electric power consumption by providing a means for disconnecting a main memory region and an output line. CONSTITUTION:This device has the means 7 for disconnecting the main memory 1 and a common data line which is the output line. The output of an address comparator circuit 11 is inputted to a switch, i.e., the means 7 and a redundancy word drive 2. The address comparator circuit 11 is so programmed that the switch 7 is on and the redundancy word drive 15 is off at the time of non-relief and hat the switch 7 is off and the redundancy word drive 15 is on at the time of relief. The data of the ordinary line and redundancy line are outputted according to the relief and the non-relief without adding the signal for an inhibit operation to an ordinary line decoding circuit (X decoder 104), namely, without inhibiting the rising operation of the line where a defect exists. The high-speed defect relief is executed with the low electric power consumption in this way.

3. 发明专利

JP2007080283A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2007080283A
公开(公告)日：2007-03-29
申请号：JP2006293469
申请日：2006-10-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKAYAMA MICHIAKI , SAKAKIBARA HIDEKI , KOBAYASHI TORU , MIYAOKA SHUICHI , YOKOYAMA YUJI , SAWAMOTO HIDEO , KUME SHOJI
IPC分类号： G06F12/00 , G06F12/08 , G11C11/406
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which easily accepts a write access request regardless of an internal memory operational status. SOLUTION: A semiconductor integrated circuit (1) includes a plurality of memory banks (BNK0-BNK7) formed on a semiconductor chip (1A), a plurality of write buffers (WB0-WB3), an external input circuit (I/F1) and a control circuit (MCNT). Each of the plurality of memory banks includes a data input part and a plurality of memory cells periodically requiring stored data refreshing operations. The control circuit controls a corresponding write buffer so as to selectively hold data supplied to the external input circuit in the corresponding write buffer during a period of time for the refresh operation and the read operation of a corresponding memory bank, and control the corresponding write buffer to supply data to the corresponding memory bank after the completion of the refresh operation and the read operation of the corresponding memory bank. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种容易接受写访问请求的半导体集成电路，而不管内部存储器操作状态如何。解决方案：半导体集成电路（1）包括形成在半导体芯片（1A）上的多个存储体（BNK0-BNK7），多个写入缓冲器（WB0-WB3），外部输入电路（I / F1）和控制电路（MCNT）。多个存储体中的每一个都包括周期性地要求存储的数据刷新操作的数据输入部分和多个存储器单元。控制电路控制相应的写入缓冲器，以便在对应的存储体的刷新操作和读取操作的时间段期间选择性地保持提供给相应写缓冲器中的外部输入电路的数据，并且控制对应的写入缓冲器在完成刷新操作和对应的存储体的读取操作之后向对应的存储体提供数据。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2000268600A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2000268600A
公开(公告)日：2000-09-29
申请号：JP7116499
申请日：1999-03-17
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KATAYAMA MASAHIRO , MIYAOKA SHUICHI , YOKOYAMA YUJI
IPC分类号： G11C11/401 , G01R31/28 , G11C29/00 , G11C29/02 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor memory that can shorten the test time in the test of a memory section. SOLUTION: This device is a logic mixedly loading memory LSI onto which a memory section 1 and a logic circuit section 2 by SDRAM are loaded, at the time of setting a test mode, an input/output terminal of a control signal allotted to the logic circuit 2 is made to function as an input terminal 3a of a RAS signal, an internal CAS signal is automatically generated a fixed time after a RAS signal is inputted to this input terminal 3a, a row address signal is taken in using a RAS signal, a column address signal is taken in using an internal CAS signal, a specified memory cell in a memory cell array of the memory section 1 is selected by these signals, and read-out or write-in of data can be performed for this selected memory cell. In this test mode, operation can be performed with one clock per one cycle.

5. 发明专利

JPH03216892A SEMICONDUCTOR MEMORY AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH03216892A
公开(公告)日：1991-09-24
申请号：JP1094690
申请日：1990-01-20
申请人： HITACHI LTD
发明人： YAMAUCHI TATSUMI , IWAMURA MASAHIRO , AKIOKA TAKASHI , HIRAISHI ATSUSHI , YOKOYAMA YUJI , KOBAYASHI YUTAKA , IDE AKIRA
IPC分类号： G11C11/417 , G11C11/409
摘要： PURPOSE:To shorten the time of data write to a memory cell by cutting off the data line of the selected memory cell and a common read line at the time of writing data in the memory cell. CONSTITUTION:Data lines of memory cells of plural columns which are omitted in the figure are connected to a common read line 10 and a common write line 11 through read transfer gates 103(M3) and 104(M4) and write transfer gates 101(M1) and 102(M2). Consequently, read transfer gates 103(M3) and 104(M4) can be forcibly turned off by a write control signal the inverse of w, and data written in a pair of data lines D and the inverse of D is not propagated to the common read line 10 at the time of data write. That is, since the potential of the common read line is not changed by data write, the overall capacity charged to and discharged from a load is reduced at the time of write to shorten the write time.

6. 发明专利

JPH03105799A REDUNDANCY MEMORY DEVICE AND DEFECT MEMORY RELIEVE SYSTEM 失效
公开(公告)号：JPH03105799A
公开(公告)日：1991-05-02
申请号：JP24212589
申请日：1989-09-20
申请人： HITACHI LTD
发明人： AKIOKA TAKASHI , YOKOYAMA YUJI , HIRAISHI ATSUSHI , IWAMURA MASAHIRO , KOBAYASHI YUTAKA , YAMAUCHI TATSUMI , TAKAHASHI SHIGERU , MOTOHASHI KOICHI
IPC分类号： G11C29/00 , G11C11/401 , G11C29/04
摘要： PURPOSE:To quicken the access to a redundant memory cell by providing a means generating an access inhibit signal and a means selecting a standby memory cell array when a defect memory cell in a block is accessed to each of plural blocks. CONSTITUTION:An address signal 8 outputted from an address buffer 1 designates an address of a memory cell of a memory cell array 4 of each block. The position of a defect memory cell provided to a prestage of an X decoder 2 and a Y decoder 5 is programmed and inputted to a redundancy program circuit 6. When the address of the defect memory cell is inputted, the redundancy program circuit 6 inputs a defect memory cell access suppression signal to the Y decoder 5 to suppress the access of the defect memory cell. Moreover, a redundancy memory cell array access signal selecting a redundancy memory cell array 7 is generated in the redundancy program circuit 6 to relieve the defect memory. Thus, the accessing to the redundancy memory cell is quickened.

7. 发明专利

JP2002352582A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2002352582A
公开(公告)日：2002-12-06
申请号：JP2001158449
申请日：2001-05-28
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： AKASAKI HIROSHI , MIYAOKA SHUICHI , YOKOYAMA YUJI , HASEGAWA MASATOSHI , KURITA KOZABURO
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C29/04 , G11C29/00
摘要： PROBLEM TO BE SOLVED: To achieve high speed operation by shortening a total delay time from input to output of a signal in a semiconductor integrated circuit device incorporating a macro-cell (circuit block which can be designed independently) such as a storage circuit and operating synchronously with an external clock. SOLUTION: In a semiconductor integrated circuit device having first circuit blocks (131, 141, 132, 142) receiving an input signal responding to a first timing signal (ϕ1) based on a clock signal (CLK) and a plurality of circuit blocks comprising a second circuit block (110) forming an output signal responding to a second timing signal (ϕ2) based on the clock signal and coupled while having serial relation about transmitting a signal, and whole operation is regulated by the clock signal, time difference between the first timing signal and the second timing signal is set so as to be a period of non-integral multiple to a period of the clock signal.

8. 发明专利

JPH06162765A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH06162765A
公开(公告)日：1994-06-10
申请号：JP33803192
申请日：1992-11-25
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： MAEDA TOSHIO , YOKOYAMA YUJI
IPC分类号： G11C11/407 , G11C11/401 , G11C11/409
摘要： PURPOSE:To accelerate the operation speed by providing a switch means to set the transmission timing of a write signal, thereby shortening the cycle time in the write mode of a dynamic RAM (DRAM) or the like. CONSTITUTION:In the DRAM or the like of the address non-multiplex system P-channel MOSFETs P1 and P2 are provided between unit amplifying circuits USA0 to USAn of a sense amplifier SA and corresponding complimentary bit lines B0T to BnT and B0B to BnB of a memory array MARY. Then, they are selectively turned off when a write signal is transmitted from a write amplifier WA through common data lines W10B and W10T for write. Therefore, the write signal transmission timing can be set just before unit amplifying circuits USA are set to the operating state. Thus, the time in which the write signal supplied to the common data line W10 reaches a desired level is shortened to accelerate the operation speed.

9. 发明专利

JPH06111574A WRITING CIRCUIT AND SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH06111574A
公开(公告)日：1994-04-22
申请号：JP25493792
申请日：1992-09-24
申请人： HITACHI LTD
发明人： YOKOYAMA YUJI , MIYAZAWA KAZUYUKI , MIWA HITOSHI
IPC分类号： G11C11/409 , G11C11/401
摘要： PURPOSE:To attain a high speed for a writing circuit and the semiconductor storage device including it. CONSTITUTION:Switching elements T10, T11 and S10 are provided between the outputs 12 and 14 of the driving logic circuit section D10 and D11 of the writing circuit and writing lines WIO and WIOB. The output level of the driving logic circuit section is set on a specified value beforehand at a standby time and only the outputs 12 and 14 of the driving logic circuit section D10 and D11 to be activated at the time of an operation are changed from the specified value. Thus, since large power and voltage are supplied for the driving logic circuit at the start of the operation, the current driving capacity of a driving element is increased and time for writing is shortened.

10. 发明专利

JPH03283668A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH03283668A
公开(公告)日：1991-12-13
申请号：JP8450390
申请日：1990-03-30
申请人： HITACHI LTD
发明人： NAMETAKE MASATAKE , KOBAYASHI YUTAKA , HIRAISHI ATSUSHI , AKIOKA TAKASHI , YOKOYAMA YUJI , IWAMURA MASAHIRO , TAKAHASHI SHIGERU , UCHIDA HIDEAKI , IDE AKIRA
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/088 , H01L29/78 , H03K17/08 , H03K19/003
摘要： PURPOSE:To protect a switching element even when static electricity is impressed on a terminal of a semiconductor integrated circuit and thereby to prevent a damage of the integrated circuit by providing the switching element with a means of protection from electrostatic breakdown. CONSTITUTION:A P well region 6 is formed on a P type semiconductor substrate 1 and a field insulation film 8 is formed. Element isolation is made by this insulation film 8 and a channel stopper region. Next, a gate insulation film 16 is formed and a gate electrode 17 is formed in the prescribed upper part thereof. High-concentration impurity regions 9 (n ) of a drain and a source are formed by doping an n-type impurity (P or As) before a side wall spacer 18 is formed, or by doping such an n-type impurity as P having a high diffusion coefficient after the side wall spacer 18 is formed. By impressing a supply voltage on an n-type semiconductor region 7, besides, a charge is neutralized in the region 7 even when a negative potential is impressed on the drain.

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