专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH0816486A LSI FOR DEFECT REMEDY AND MEMORY DEVICE 失效
公开(公告)号：JPH0816486A
公开(公告)日：1996-01-19
申请号：JP17020794
申请日：1994-06-29
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： WADA SHOJI , KEMIZAKI KANEHIDE , MURANAKA MASAYA , OGATA SHINKO , AOYANAGI HIDEAKI , KITAME TETSUYA , KATAYAMA MASAHIRO , KUBONO SHIYOUJI , SUZUKI YUKIE , MORINO MAKOTO , MIYATAKE SHINICHI , HARUFUJI SEIICHI , KOYAMA YOSHIHISA , ONO NOBUHIKO
IPC分类号： G06F12/16 , G11C29/00 , G11C29/02 , G11C29/44 , H01L21/82
摘要： PURPOSE:To provide an LSI which can remedy a defect of a mounted DRAM and to provide a memory device which can remedy the defect of the DRAM generated after assembly. CONSTITUTION:The LSI for defect remedy consists of an interface part for the same address and control with DRAMs, an input/output interface corresponding to the memory device consisting of plural DRAMs, a nonvolatile storage circuit 3 which stores the chip addresses of the DRAMs and a defect address of an X system, a RAM part 4 for redundancy remedy consisting of an SRAM which has a word line selected with a comparison matching signal between an inputted X address and the defect address of the storage circuit and a column selected with a Y address signal, a selection part 6 which connects the data input/output bus of the RAM part for redundancy to a data input/output terminal, a data input/output part 7 which activates an input/output circuit corresponding to the selection, and a mask part 8 which outputs a signal for placing the output terminal of a DRAM judged to be defective in a high-impedance state.

2. 发明专利

JPH07176698A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH07176698A
公开(公告)日：1995-07-14
申请号：JP34415293
申请日：1993-12-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KUBONO SHIYOUJI , KUME HITOSHI
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/10 , G11C16/30 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L29/788 , H01L29/792
摘要： PURPOSE:To obtain a power supply circuit for forming a plurality of types of inner voltages highly accurately and efficiently by providing a circuit for controlling a charge pump circuit intermittently to produce a desired inner voltage equal to the sum of (n) times of a specific voltage and a predetermined divided voltage. CONSTITUTION:The semiconductor integrated circuit device comprises a reference voltage generating circuit and a selector 1 receives a plurality of voltages VRSI required for formation of a voltage VEG among voltages VRSi being set with reference to the ground potential of the circuit. The selector 1 selects one voltage designated by a trimming circuit 3 and delivers the selected voltage to a booster circuit. The booster circuit is controlled intermittently by a control circuit to produce an output voltage VEG which is equal to the sum of (n) times of selected voltage VRSI and a voltage VRSK selected among the voltages VRSi through the connection.

3. 发明专利

JPH0697797A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0697797A
公开(公告)日：1994-04-08
申请号：JP26807592
申请日：1992-09-10
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KUBONO SHIYOUJI , FUJII ISAMU
IPC分类号： G11C11/407 , H01L21/8242 , H01L27/10 , H01L27/108 , H03K17/22
摘要： PURPOSE:To provide the semiconductor integrated circuit having a voltage detection circuit which makes the stable operation possible regardless of the rising speed of the power supply voltage and realizes the voltage detection without increasing the power consumption of a substrate voltage generation circuit. CONSTITUTION:A current source 12 is provided at the other electrode of a capacitor C2 connected to a power supply Vcc. The voltage of the capacitor C2 is supplied to a gate and a source to control a M0SFETQ 14. The drain and a ground Vss are connected by a capacitor C3 and the power supply voltage transition detection is performed based on the voltage. Transistors Q15, Q17 and Q16, Q19 constructing a current mirror circuit supplying bias current to each drain are installed. A transistor 18 is connected between the drains of the transistor Q17 and the transistor Q19. The gate of the transistor is used for detecting the fluctuation of substrate voltage Vss. The fluctuation is shown in the drain of the transistor 16 through the current mirror circuit.

4. 发明专利

JPH0628849A DYNAMIC TYPE RAM 失效
公开(公告)号：JPH0628849A
公开(公告)日：1994-02-04
申请号：JP20722792
申请日：1992-07-11
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KUBONO SHIYOUJI , KOYAMA YOSHIHISA
IPC分类号： G11C11/403 , G11C11/401 , G11C11/406
摘要： PURPOSE:To allow a dynamic type cell memory to hold information with a high reliability by providing a tire circuit at a part where heat radiating condition is bad on a semiconductor substrate. CONSTITUTION:A tire circuit 4 is provided at the central part of a semiconductor chip 1 on the worst condition of the radiation of heat. When a dynamic type RAM is switched from an operating state to a data holding mode (automatic refresh mode), the part remains to be a high temperature until the end of a temperature distribution generated by the chip 1. Then, a refresh cycle corresponding to the high temperature is decided by arranging the tire circuit 4 at the pertinent part. Therefore, it is not necessary to set the refresh cycle longer than the refresh time of the memory cell arranged at an area where the radiating condition is satisfactory.

5. 发明专利

JPS63142591A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS63142591A
公开(公告)日：1988-06-14
申请号：JP28885486
申请日：1986-12-05
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MURANAKA MASAYA , YOSHIDA MASAHIRO , KUBONO SHIYOUJI
IPC分类号： G11C11/401 , G11C11/34
摘要： PURPOSE:To attain simplified picture system and low cost by providing a row address generating circuit in a dual port memory thereby having only to supply a serial clock signal externally. CONSTITUTION:A final row address signal supplied externally via a row address buffer RADB is inputted to an address detection circuit RAD via a row address register RAR of a row address generating circuit RAG. Moreover, a row address counter RAC supplies a data transfer row address signal advanced at each data transfer cycle to an address multiplexer AMX and supplies it to the circuit RAD. The circuit RAD compares signals from the counter RAC and the register RAR and when they are coincident, a final address signal syn is sent to a timing control circuit TC via an AND gate circuit AG. Thus, the word line within the designated range is designated sequentially to continue the input/output operation thereby attaining simplicity and low cost.

6. 发明专利

JPH0964699A OSCILLATION CIRCUIT, SEMICONDUCTOR STORAGE DEVICE USING THE OSCILLATION CIRCUIT AND COMPUTER SYSTEM USING THE STORAGE DEVICE 失效
公开(公告)号：JPH0964699A
公开(公告)日：1997-03-07
申请号：JP21996595
申请日：1995-08-29
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KANEMITSU MICHITARO , KUBONO SHIYOUJI
IPC分类号： G11C11/407 , G11C16/06 , G11C17/00 , H01L21/8234 , H01L27/088 , H03K3/0231 , H03K4/02
摘要： PROBLEM TO BE SOLVED: To provide an oscillation circuit capable of reducing a layout area by realizing a constant current circuit consisting of a low resistor element, reducing power supply voltage dependency and shortening rise time at the starting. SOLUTION: The oscillation circuit generates an output signal with a prescribed oscillation period by oscillation operation repeating the charge and discharge of a capacitor element. The oscillation circuit is constituted of a constant current circuit 1 consisting of a depression type MOS FET Q1, a resistor R1 having a small resistance value and enhancement type MOS FETs Q2 to Q4, enhancement type MOS FETs Q5 to Q7, a capacitor C1, a differential amplifier circuit CMP 2, a delay circuit 3, and a booster circuit 4. The circuit 2 compares a constant voltage level generated from the circuit 1 with the voltage level of the capacitor C1 and the capacitor C1 is charged or discharged in accordance with the compared result.

7. 发明专利

JPH05341867A 失效
公开(公告)号：JPH05341867A
公开(公告)日：1993-12-24
申请号：JP17020292
申请日：1992-06-04
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KUBONO SHIYOUJI
IPC分类号： G05F3/24 , G05F3/26
摘要： PURPOSE:To obtain an arbitrary reference voltage high precisely set by a simple circuit by adjusting the difference of the threshold voltage or the constant voltage of the first and third MOSFET according to the size rate of the first and second(third and forth) MOSFET. CONSTITUTION:A MOSFET Q1 and a MOSFET Q3 are a current mirror configuration. Currents of the same value are running through MOSFET Q3 and Q4, or MOSFET Q1 and Q2. Then, the threshold value increased in a process of the MOSFET Q1, or the added voltage of the threshold voltage to the constant voltage of the MOSFET Q1 is supplied between the gate and source of the MOSFET Q3. The MOSFET Q2 and Q4 are the same conductive MOSFET, and allowed to have the same threshold currents. The size rate of the MOSFET Q1 and Q2 is set to be the same as the size rate of the MOSFET Q3 and Q4. The difference of the voltage between the gate and source of the MOSFET Q2 and Q4 is used as the reference voltage. Thus, the arbitrary reference voltage can be obtained.

8. 发明专利

JPH05101649A RAM WHICH FOLLOW UP POWER SOURCE FLUCTUATION AT HIGH SPEED 失效
公开(公告)号：JPH05101649A
公开(公告)日：1993-04-23
申请号：JP25886991
申请日：1991-10-07
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KUBONO SHIYOUJI
IPC分类号： G11C11/404
摘要： PURPOSE:To divide the voltage of a plate between a power source and the ground by a parasitic capacity so that the RAM can follow up the fluctuation in power source voltage at a high speed by adding the parasitic capacity equiv. to the parasitic capacity between the plate to serve as a reference level of a memory cell capacitor and the ground potential. CONSTITUTION:A conductive layer 11 consisting of a gate wiring is provided between the plate 8 and a bit line 9 consisting of an aluminum layer and is connected to a power source Vcc. The parasitic capacity C2 generated between the plate layer 8 and the power source Vcc at this time has the capacity of the sum of the parasitic capacity generated between the plate layer 8 and the bit line 9 and the parasitic capacity generated between the bit line 9 and the power source Vcc. The plate level attains the potential divided by the series resistance and the parasitic capacity between the power source and the ground when this method is applied to a memory cell of a DRAM type, thereby the delay by the CR is suppressed. The plate level follows up the fluctuation in the power source Vcc at the high speed even if the power source fluctuates at the time of data retention. The wait time for the power source fluctuation is thus shortened.

9. 发明专利

JPH0442491A CMOS INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0442491A
公开(公告)日：1992-02-13
申请号：JP15129490
申请日：1990-06-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KEMIZAKI KANEHIDE , KUBONO SHIYOUJI , MOCHIZUKI TOSHIO , SATO KATSUYUKI
IPC分类号： G11C11/407 , G11C11/401 , G11C11/403
摘要： PURPOSE:To obtain the CMOS integrated circuit which can operate by voltage composed of plural kinds of batteries by limiting only the voltage with plural kinds of batteries whose maximum value is limited to about 3.6V as operational voltage. CONSTITUTION:Memory access can be performed based on the supply of the voltage generated by the battery composed of the plural kinds of batteries whose maximum value is limited to 3.6V, a RAM composed of plural numbers 1 or N is included, and a logical level in an input/output interface is set to satisfy a technology standard for a CMOS circuit with low voltage. Namely, a circuit element constituting the RAM and a control circuit is constituted based on the battery voltage whose maximum voltage is 3.6V. Thus, the RAM with CMOS construction which can perform the memory access with these plural kinds of batteries can be obtained.

10. 发明专利

JPH02187987A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH02187987A
公开(公告)日：1990-07-24
申请号：JP803489
申请日：1989-01-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO KATSUYUKI , KAJIMOTO TAKESHI , SHINPO YUTAKA , KEMIZAKI KANEHIDE , OGATA SHINKO , KUBONO SHIYOUJI , MANITA KIICHI
IPC分类号： G11C11/403 , G11C11/401 , G11C11/406 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To contrive the realization of low power consumption by setting the number of simultaneous selection of word lines in a self-refresh mode of a pseudo static type RAM, etc., to integer multiple of a regular mode and setting a refresh period in the self-refresh mode to integer multiple. CONSTITUTION:At the time of a self-refresh mode, eight pieces of memory arrays MARY0L-3L and 0R-3R corresponding to all memory a mats MAT0-3 are brought to operating state simultaneously, and refresh operations of eight pieces of word lines are executed simultaneously, executed autonomously and periodically by four folds of a prescribed refresh period, and a refresh address counter RFC is updated each time. The lower 2 bits of the counter RFC is fixed to logic '0', and only the upper 9 bits are updated. In such a way, the number of times of a refresh operation per unit time in a self-refresh mode of a pseudo static type RAM is curtailed, by which an average operating current is curtailed remarkably and low power consumption can be realized.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式