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1. 发明专利

JPH06333392A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH06333392A
公开(公告)日：1994-12-02
申请号：JP11813293
申请日：1993-05-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI YUKIE , NAKAI KIYOSHI , MURANAKA MASAYA
IPC分类号： G11C11/409 , G11C11/401
摘要： PURPOSE:To suppress the influence of decreasing a power source voltage affecting the margin of reading operation and an access time and to enhance the voltage lowering of a dynamic RAM, etc. CONSTITUTION:The effective level of a pre-charging control signal PCSO supplied to the gate of a pre-charging MOSFET N9 is made to be a high voltage VCH immediately after a dynamic RAM is made a non-selection state from its selection state so as to make the corresponding memory array an active state and made to become the power source voltage VCC during the period in which the corresponding memory array is made the active state after the dynamic RAM is again made the selection state. At the beginning of the non- selection state of the dynamic RAM, the voltage between the gate and the source of the MOSFET N9 is increased and the equalizing operation of a complementary bit line is surely performed at high speed. During the period in which the corresponding memory array is made the active state after the dynamic RAM is again made the selection state, the potential of the pre-charging control signal is lowered earlier down to the power source voltage VCC and the MOSFET N9 is quickly turned off.

2. 发明专利

JPH03205698A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH03205698A
公开(公告)日：1991-09-09
申请号：JP55790
申请日：1990-01-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MURANAKA MASAYA
IPC分类号： G11C29/00 , G11C11/401 , G11C29/04 , H01L21/82 , H01L27/10
摘要： PURPOSE:To stably and surely decide whether a defect is relieved or not by reversing the direction of the current change of an external terminal between the redudancy relief state and the redundancy non-relief state in response to the control of switching from the first operation mode to the second operation mode. CONSTITUTION:When a control signal phiren is in the low level, a control signal phisig is first in the low level and is changed to the high level. When the relief signal, namely, the control signal phiren is in the high level, the control signal phisig is first in the high level and is changed to the low level. Consequently, the direction of the current change of a data input/output terminal 10 is reversed between the redundancy relief state and the redundancy non-relief state in response to switching from the normal mode to the test mode when the operation mode is first set to the normal mode and is switched to the test mode at the time of applying a prescribed voltage higher than a supply voltage Vdd to the data input/output terminal 10. Thus, it is stably and surely decided whether a defect is relieved by redundancy or not.

3. 发明专利

JPH01278065A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH01278065A
公开(公告)日：1989-11-08
申请号：JP10874888
申请日：1988-04-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI YUKIE , MURANAKA MASAYA , ISHIHARA MASAMICHI
IPC分类号： G11C29/00 , G11C29/50 , H01L21/66 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To make it possible to measure a signal waveform in a dense region, with high S/N ratio by connecting a data line or a word line with a measuring terminal for an electron beam tester being formed by using a final wiring layer upper than the data line or the word line. CONSTITUTION:A data line 18 or a word line 7, at least, is connected with a measuring terminal 21 for an electron beam (EB) tester formed by using a final wiring layer upper than the data line or the word line. Said measuring terminal 21 for the EB tester is formed by using the same conducting layer as the word line 7 or the data line 18. Thereby, the measuring terminal 21 can be connected with a data line 18 or the word line 7 by using the smallest size. As a result, the measuring terminal 21 can be arranged in a dense region where the data line 18 or the word line 7 is arranged, so that the measurement of signal waveform with high S/N ratio is enabled.

4. 发明专利

JPS6379298A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS6379298A
公开(公告)日：1988-04-09
申请号：JP22357986
申请日：1986-09-24
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： MURANAKA MASAYA , MATSUURA NOBUMI , KEMIZAKI KANEHIDE , OKAYAMA OSAMU
IPC分类号： G11C11/401 , G11C8/00 , G11C29/00 , G11C29/04 , G11C29/42
摘要： PURPOSE:To identify the concrete content of a defect by comparing a defective address with an address designated externally and inhibiting the operation of a redundanty address switching circuit switching to a standby memory array when they are coincident thereby accessing the defective memory cell intensionally. CONSTITUTION:AND gate circuits AG1-AG4 are provided between standby word line drive circuits RWD0-RWD3 corresponding to address comparison circuits AC0-AC3 of a redundant address switching circuit RAC. Then the output signal is sent to the standby word line drive circuits RWD0-RWD3 corresponding selectively to a redundant address enable signal RAE supplied externally to bring the signal RAE to inhibit the switching to the standby memory array by the switching circuit RAC. Thus, a fail bit map is produced forcibly for the statistic investigation and fault analysis about the state of occurrence of defects.

5. 发明专利

JPS62165247A INFORMATION PROCESSING SYSTEM 失效
公开(公告)号：JPS62165247A
公开(公告)日：1987-07-21
申请号：JP646686
申请日：1986-01-17
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： KAZUUJI KAZUO , MURANAKA MASAYA
IPC分类号： G06F12/00 , G06T1/60
摘要： PURPOSE:To make a system simple and make the quick data processing almighty by providing a controller which detects address designation corresponding to designation of the operation mode of a peripheral device and generates a control signal which instructs the peripheral device to take in the operation mode. CONSTITUTION:When a write signal DB supplied fro an external terminal Di is taken in through a data input circuit IB and an operation mode signal fn instructs the AND operation mode, a logical operation circuit LU generates an AND signal DA.DB between a signal DA of a latch circuit F and a write signal DB and transmits it to an input/output node I/O. The signal DA.DB is written in a selected memory cell, and stored information of the memory cell is substituted with picture element data according with the logical operation between this information and the write signal supplied from an external terminal by the write operation of one cycle. Thus, an address space for setting of the operation mode different from the address space of the peripheral device and this provided address space is addressed to easily perform the setting operation of the operation mode of the peripheral device.

6. 发明专利

JPH04318392A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04318392A
公开(公告)日：1992-11-09
申请号：JP8497091
申请日：1991-04-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MURANAKA MASAYA , SUZUKI YUKIE
IPC分类号： G11C11/407 , G11C11/401 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To realize high speed driving of a word line without reducing the reliability and the yield of the semiconductor integrated circuit device which has a DRAM circuit region. CONSTITUTION:A memory mat 1 of DRAM is divided into plural minute memory cell regions 2, word line driving circuit regions WD1 and WD2 are dispersedly placed for each minute memory cell region 2 by surrounding it and each of the word line driving circuit located within the word line driving circuit regions WD1 and WD2 is connected to the minute memory cell region 2 by a word line WL which consists of low resistance polysilicon.

7. 发明专利

JPH02234460A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02234460A
公开(公告)日：1990-09-17
申请号：JP5386589
申请日：1989-03-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MATSUURA NOBUMI , KIZAKI TAKESHI , MURANAKA MASAYA
IPC分类号： H01L27/04 , G11C11/401 , G11C11/408 , H01L21/822
摘要： PURPOSE:To facilitate layout of substrate potential generating circuits by a method wherein a plurality of the substrate potential generating circuits are separately arranged on a semiconductor chip to supply the substrate potential. CONSTITUTION:For instance, four substrate potential generating circuits VBG1-VBG4 are arranged separately on the four corners of a semiconductor chip 1. In this case, parameters of elements of which the four respective substrate potential generating circuits VBG1-VBG2 are composed are so determined as to satisfy the total potential supply capacity by the four circuits. With this constitution, the occupied areas of the four respective substrate potential generating circuits, can be reduced, their layout can be designed easily and, further, the vacant spaces of the chip can be so arranged to be utilized efficiently, so that the increase of the chip size be suppressed.

8. 发明专利

JPS63197099A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS63197099A
公开(公告)日：1988-08-15
申请号：JP2827687
申请日：1987-02-12
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MURANAKA MASAYA , KUBONO SHIYOUJI
IPC分类号： G11C17/18 , G11C16/06 , G11C17/00
摘要： PURPOSE:To shorten an access time by providing sense amplifiers at every plural memory cell columns, previously reading out plural data so as to hold them in the sense amplifiers and reading out desirable data from the sense amplifier by switching a switch. CONSTITUTION:The common sense amplifiers SA are respectively provided at every specified number of memory cell MC columns and one sense amplifier is selected from the sense amplifiers SA and connected to a main amplifier MA. In the case of a remarkable address transition such as one where the data held in the sense amplifier SA is changed a signal which informs it to outside is outputted. Since the data in plural memory cells MC can be read out to be held in the sense amplifier SA at the same time, the data can be directly obtained only by switching the selection switch QS in the case of reading out the desirable data from the data held in the sense amplifiers SA. Thus, the accessing time can be shortened.

9. 发明专利

JPH0917178A SEMICONDUCTOR STORAGE AND MEMORY SYSTEM 失效
公开(公告)号：JPH0917178A
公开(公告)日：1997-01-17
申请号：JP9479796
申请日：1996-03-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MURANAKA MASAYA , MIYATAKE SHINICHI , SUZUKI YUKIE , KITAME TETSUYA , MORINO MAKOTO , KEMIZAKI KANEHIDE
IPC分类号： G11C11/403 , G11C7/04 , G11C7/10 , G11C11/406 , G11C11/4096 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor storage and a memory system which has a reliable data-retaining function with a simple configuration and can drastically reduce the power consumption in a data retention mode. SOLUTION: Two memory cells of different memory arrays ARRAY 1 and ARRAY 2 are simultaneously selected by specifying a specific write operation mode to making the logic 1 of a write signal correspond to a state where a capacitor is charged and the logic 0 of the write signal correspond to a state where the capacitor is not charged, thus writing a same write signal. Then, by specifying a specific read-out operation mode, two dynamic-type memory cells of the different memory array are simultaneously selected, a state where the capacitor of the dynamic-type memory cell is charged or not is made to correspond to the logic 1 or 0 of the read-out signal corresponding to the write operation, and the same time the logic 1 of the read-out signal is outputted preferentially.

10. 发明专利

JPH07130174A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07130174A
公开(公告)日：1995-05-19
申请号：JP30236193
申请日：1993-11-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KIKUCHI KAZUE , MURANAKA MASAYA
IPC分类号： G11C11/41 , G11C11/407 , G11C11/408
摘要： PURPOSE:To suppress the fluctuation of a delay time by constituting parts affecting to the delay times of delay circuits and extending a difference between a power source voltage and a threshold voltage due to the making of a low power source voltage. CONSTITUTION:P channel MOSFETs P1 to 3 P5, P6, P8, P9 constituting an inverter V2, anodes N07, NO8 affecting to the delay time of the delay circuit of a pulse width setting circuit PWT1 and N channel MOSFETs N2 to 4, N7 TO 9 constituting inverters V3, V4 are made to be low threshold value voltage type MOSFETs. Moreover, in a pulse width setting circuit PWT2, an inverter V6, anodes N09, 10 are constituted of P channel MOSFETs and inverters V7,V8 are constituted of N channel MOSFETs. Further, FETs P10 to 13, N12 to 15 are also made to be low threshold value voltage type FETs. Thus, the difference between the power source voltage and the threshold voltage which is compressed by the making of a low power source voltage is extended and the ocupying ratio of the fluctuation amount of the power source voltage and the threshold voltage with respect to the differential amount is made small.

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