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1. 发明专利

JPH01164138A DIAGNOSTIC SYSTEM FOR STUFF MULTIPLEXING DEVICE 失效
公开(公告)号：JPH01164138A
公开(公告)日：1989-06-28
申请号：JP32131787
申请日：1987-12-21
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： SAKAKIDA HISAHIRO , SHINADA SHIGEO , KOSUGE SHOJI , NAKAMURA TATSUYA
IPC分类号： H04J3/14
摘要： PURPOSE:To diagnose the function of a device stably and moreover through simple and easy circuit constitution even if jitter exists by controlling a counting operation in a write/read address counter by a prescribed way prior to diagnosis. CONSTITUTION:The phase comparison circuit 18 of a destuff circuit in a diagnosis circuit is operated prior to the diagnosis, and the counting operation of the write/read address counters 16,17 is controlled. Namely, for instance, in a case that the reference phase of the write address counter 16 leads that of the read address counter 17 and the phase difference of them is smaller than a prescribed value (value larger than allowable jitter width), the counting operation of the read address counter 17 is stopped for one bit so as to make the phase difference larger by one bit. Thus, a write address and a read address come to have the phase difference larger than the prescribed difference whichever is made to be a standard, and since a sufficient phase allowance is secured prior to the diagnosis, the function of the device can be diagnosed stably and moreover through the simple and easy circuit constitution even if the jitter is contained in input data.

2. 发明专利

JPS62160834A AIS SIGNAL RECEPTION CIRCUIT 失效
公开(公告)号：JPS62160834A
公开(公告)日：1987-07-16
申请号：JP202586
申请日：1986-01-10
申请人： HITACHI LTD
发明人： KITAZAWA MASAKAZU , KOSUGE SHOJI
IPC分类号： H04J3/14 , H04L1/00 , H04L25/02
摘要： PURPOSE:To prevent reception mis-decision of an AIS signal by setting the initial value of a synchronizing counter in response to the state of a reception data so as to count accurately number of '0' signals in the reception data. CONSTITUTION:The synchronizing counter comprising gate combination circuits 1, 3 and FFs 2, 4 synchronizes a reception clock CLK and is set to an initial value at the generation of a synchronizing pulse and counts up by using a '0' signal in a reception data DATA. When an AIS reception discrimination period elapse and the next synchronizing pulse is generated, the initial value is set again in response to the state of the reception data. A NAND gate 5 decodes the case that number of '0' signals from the synchronizing counter is

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