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1. 发明专利

JPH01164138A DIAGNOSTIC SYSTEM FOR STUFF MULTIPLEXING DEVICE 失效
公开(公告)号：JPH01164138A
公开(公告)日：1989-06-28
申请号：JP32131787
申请日：1987-12-21
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： SAKAKIDA HISAHIRO , SHINADA SHIGEO , KOSUGE SHOJI , NAKAMURA TATSUYA
IPC分类号： H04J3/14
摘要： PURPOSE:To diagnose the function of a device stably and moreover through simple and easy circuit constitution even if jitter exists by controlling a counting operation in a write/read address counter by a prescribed way prior to diagnosis. CONSTITUTION:The phase comparison circuit 18 of a destuff circuit in a diagnosis circuit is operated prior to the diagnosis, and the counting operation of the write/read address counters 16,17 is controlled. Namely, for instance, in a case that the reference phase of the write address counter 16 leads that of the read address counter 17 and the phase difference of them is smaller than a prescribed value (value larger than allowable jitter width), the counting operation of the read address counter 17 is stopped for one bit so as to make the phase difference larger by one bit. Thus, a write address and a read address come to have the phase difference larger than the prescribed difference whichever is made to be a standard, and since a sufficient phase allowance is secured prior to the diagnosis, the function of the device can be diagnosed stably and moreover through the simple and easy circuit constitution even if the jitter is contained in input data.

2. 发明专利

JPS63299421A PLO ABNORMALITY DETECTION CIRCUIT 失效
公开(公告)号：JPS63299421A
公开(公告)日：1988-12-06
申请号：JP13110587
申请日：1987-05-29
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： ISHIDA KAZUTO , SAKAKIDA HISAHIRO , SHINADA SHIGEO , FUJITA HIROYUKI , TOKUNAGA KOJI , NAKATSU HIROSHI , NAKAMURA TATSUYA , HORIE KIYOSHI
IPC分类号： H04J3/07 , H04J3/14
摘要： PURPOSE:To easily detect the abnormality of a PLO, by comparing the write address and the read address of a buffer memory to convert data to asynchronous data, and detecting the disappearance of a difference between both address counters and the superposotion of addresses. CONSTITUTION:In the normal operation of the PLO 7, no superposition of the write address A and the read address B occurs, and the data is read out normally form the buffer memory 3 synchronizing with a smoothed clock CLK and without generating slippage. The output C of a phase comparator 6 performs a toggle operation. The PLO 7 is operated so as to set the average duty factor of the waveform of the signal C at 50%, and a reading clock CLK is generated and outputted. Next, when the abnormality is generated in the PLO 7, no control to set the average duty factor of the waveform of the signal C at 50% functions, and either state that the clock with a frequency faster or slower than that in the normal operation is outputted, or, that no clock is outputted is generated.

3. 发明专利

JP2014146216A Firmware update method 审中-公开
标题翻译：固件更新方法
公开(公告)号：JP2014146216A
公开(公告)日：2014-08-14
申请号：JP2013014986
申请日：2013-01-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKAMURA TATSUYA , TODOROKI NAOYUKI , SATO TAKAHIRO , SAEKI RYOSUKE , MATSUI MASARU
IPC分类号： G06F11/00 , G06F13/10
摘要： PROBLEM TO BE SOLVED: To realize simple operations for updating firmware (F/W) in a system device comprising a plurality of independent information processing devices, that do not require network setting such as IP address setting, complicated processing, or a system control device for controlling F/W update of the plurality of information processing devices.SOLUTION: In a system device, a plurality of independent information processing devices comprise management processors (BMCs), respectively, and the BMCs of the respective information processing devices are in intercommunicative states. When firmware (F/W) update data is transmitted via a USB interface to arbitrary one of the information processing devices, the system executes F/W update processing on all of the other information processing devices.
摘要翻译：要解决的问题：为了实现用于更新包括多个独立信息处理设备的系统设备中的固件（F / W）的简单操作，其不需要诸如IP地址设置，复杂处理或系统控制设备的网络设置用于控制多个信息处理设备的F / W更新。解决方案：在系统设备中，多个独立的信息处理设备分别包括管理处理器（BMC），并且各个信息处理设备的BMC处于互通状态。当通过USB接口将固件（F / W）更新数据传送到信息处理设备中的任意一个时，系统对所有其他信息处理设备执行F / W更新处理。

4. 发明专利

JP2006123747A Supporting and output system for actual scheduling of train operation diagram, output method, and output program 审中-公开
标题翻译：火车操作图实际调度的支持和输出系统，输出方法和输出程序
公开(公告)号：JP2006123747A
公开(公告)日：2006-05-18
申请号：JP2004315189
申请日：2004-10-29
申请人： Hitachi Ltd , West Japan Railway Co , 株式会社日立製作所 , 西日本旅客鉄道株式会社
发明人： NISHI TOSHIMASA , NAKAMURA TATSUYA , KOFUCHI TAKEMASA , URATA SHINICHI
IPC分类号： B61L27/00
摘要： PROBLEM TO BE SOLVED: To make a diagram alteration through an easy, certain, and efficient procedure and present the contents of the alteration to the staff of train operation clearly and simply.
SOLUTION: The system to support and output the schedule of the actual train operation diagram are to obtain the diagram data for a plurality of days, display the train information of the date obtained on a display device 3, and support preparing the actual train diagram at the operation date by receiving the specification of the date to be operated actually within the displayed train information.
COPYRIGHT: (C)2006,JPO&NCIPI

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