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1. 发明专利

JPH02246149A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR REMEDYING DEFECT THEREOF 失效
公开(公告)号：JPH02246149A
公开(公告)日：1990-10-01
申请号：JP6583989
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI DEVICE ENG
发明人： SAKUTA TOSHIYUKI , ISHIHARA MASAMICHI , MIYAZAWA KAZUYUKI , HIROKI MASANORI , IWAI HIDETOSHI , NAKAMURA TAKASHI , TAKAHASHI YASUSHI , MAEDA TOSHIO , MATSUURA NOBUMI , HORI RYOICHI , SASAKI TOSHIO , SAKAI OSAMU , UCHIYAMA HIROYUKI
IPC分类号： G11C29/00 , G11C11/401 , G11C11/406 , G11C29/04 , H01L21/82 , H01L27/10
摘要： PURPOSE:To simplify and rationalize a layout by a method wherein a circuit having a RAM function is formed as a macrocell and a plurality of macrocells constitute a semiconductor storage circuit of a large storage capacity. CONSTITUTION:In this RAM, a plurality of memory blocks which has been formed as macrocells are arranged in a matrix manner. Sixteen memory blocks of about 4 Mbits each are arranged in four rows and four columns and have a large storage capacity of about 64 Mbits as a whole. One memory block constituted as the macrocell is provided with the following: a row-based address decoder which receives an address signal supplied through a timing/address generation circuit which have been made common; an address selection circuit composed of a word-line drive circuit, a column-based address decoder, a column selection-line drive circuit or the like; a timing generation circuit which generates a time-series timing pulse when an internal operation is required according to a memory array and an operating mode; a timing generation circuit for a selected memory cell; an input/output circuit which executes a write/readout operation of a data for the selected memory cell.

2. 发明专利

JPH02234460A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02234460A
公开(公告)日：1990-09-17
申请号：JP5386589
申请日：1989-03-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MATSUURA NOBUMI , KIZAKI TAKESHI , MURANAKA MASAYA
IPC分类号： H01L27/04 , G11C11/401 , G11C11/408 , H01L21/822
摘要： PURPOSE:To facilitate layout of substrate potential generating circuits by a method wherein a plurality of the substrate potential generating circuits are separately arranged on a semiconductor chip to supply the substrate potential. CONSTITUTION:For instance, four substrate potential generating circuits VBG1-VBG4 are arranged separately on the four corners of a semiconductor chip 1. In this case, parameters of elements of which the four respective substrate potential generating circuits VBG1-VBG2 are composed are so determined as to satisfy the total potential supply capacity by the four circuits. With this constitution, the occupied areas of the four respective substrate potential generating circuits, can be reduced, their layout can be designed easily and, further, the vacant spaces of the chip can be so arranged to be utilized efficiently, so that the increase of the chip size be suppressed.

3. 发明专利

JPS62121991A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62121991A
公开(公告)日：1987-06-03
申请号：JP26123085
申请日：1985-11-22
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： MATSUURA NOBUMI
IPC分类号： G11C11/408 , G11C11/34
摘要： PURPOSE:To improve the trackability of a power source voltage and to reduce power consumption by supplying a negative voltage formed by a capacitor through an FET controlled by a negative voltage generated complementary to the former voltage. CONSTITUTION:An inverter formed with P-type complementary FETs Q1 and Q2 and that formed with N-type complementary FETs Q3 and Q4 operate complementarily. When one electrode of the capacitor C1 connected to the FETs Q3 and Q4 with their outputs at L comes to L, a diode connection FET Q5 is turned off, and the other electrode C comes to a negative potential. An FET Q7 is turned on by the inverters Q1 and Q2 operating complementary to the inverter, the capacitor C2 connected to the inverter and the level L of a diode connection FET Q6, and the low potential of the electrode C is outputted as the back bias voltage of a substrate. With this constitution using the capacitor, the trackability of the power source voltage is improved, and the FET for controlling a negative voltage can transmit a negative potential back bias without loss. And power consumption can be reduced by making an oscillation frequency and capacitor capacity smaller.

4. 发明专利

JPH04155859A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH04155859A
公开(公告)日：1992-05-28
申请号：JP28148690
申请日：1990-10-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KOYAMA YOSHIHISA , MATSUURA NOBUMI , II HARUO , MURANAKA MASAYA , ABE JUNICHI , SUZUKI YUKIE , ARAI KOJI , YOSHIKAWA KAZUE
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L27/108
摘要： PURPOSE:To enhance an electrostatic breakdown preventive circuit in breakdown strength by a method wherein the distance between the connection region of a second semiconductor region connected to an outer terminal and the peripheral edge nearest to the connection region is set equal to or larger than the junction depth of the second semiconductor region at the connection region. CONSTITUTION:A P-type well region 3 higher than a P -type semiconductor substrate 1 in impurity concentration is formed on a first region of the primary surface of the P -type semiconductor substrate 1, and an N-type well region 2 is formed on a second region of the primary surface of the P -type semiconductor substrate 1. The N-type well region 2 forms the protective resistive element R of an electrostatic breakdown protecting circuit 30, where the one end of the element R is connected to an external terminal BP provided to the primary surface and the other end is connected to an input stage circuit 31. A distance L2 between the connection region (N -type semiconductor region 8) of the N-type well region 2 which serves as the element R of the electrostatic breakdown protective circuit 30 and the nearest periphery is set equal to or larger than the junction depth L1 of the N-type well region 2 at the connection region.

5. 发明专利

JPH0258377A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0258377A
公开(公告)日：1990-02-27
申请号：JP20843288
申请日：1988-08-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKAHASHI YASUSHI , MATSUURA NOBUMI , KOYAMA YOSHIHISA , MURANAKA MASAYA , KIMURA KATSUTAKA , IWAI HIDETOSHI , MIYAZAWA KAZUYUKI , ISHIHARA MASAMICHI
IPC分类号： H01L23/522 , G11C11/401 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To realize high speed advancement of operation speed of a semiconductor integrated circuit device having DRAM by making wiring layers at the first and second layers into the wiring layers for signal transmission which are connected electrically at every specified interval. CONSTITUTION:In DRAM1, standard clock signal generating circuits (RAS and/or CAS) which are arranged respectively on opposite short sides of a rectangular chip and address circuits (XAB, YAB) are provided extendedly along the long side of the rectangular chip and are connected with standard clock signal wires in short-circuited two-layer wiring structure. Hereby, the resistance value of the standard clock signal wiring is reduced as compared with the case of single layer wiring structure, and high speed advancement of the transmission speed of standard clock signals is achieved. Hereby, the margin of address set-up time and address hold time improves, and high speed advancement of the operation speed of the DRAM1 can be achieved.

6. 发明专利

JPS6480041A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6480041A
公开(公告)日：1989-03-24
申请号：JP23590187
申请日：1987-09-19
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKAHASHI YASUSHI , MATSUURA NOBUMI , KOYAMA YOSHIHISA , MURANAKA MASAYA , KIMURA MASATAKA , MIYAZAWA KAZUYUKI , ISHIHARA MASAMICHI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
摘要： PURPOSE:To prevent the disconnection of aluminum wiring at the second layer in a part which is stepped because of aluminum wiring at the first layer, by causing the thickness of aluminum wiring at the first layer to be thinner than that of aluminum wiring at the second layer. CONSTITUTION:Aluminum wiring Al 1 at the first layer is mounted on a layer insulation film 3 and aluminum wiring Al 2 at the second layer is mounted on the layer insulation film 4. In such a case, this device allows the thickness of wiring Al 1 to be thinner than that of wiring of Al 2. Then, a stepped part which is caused by wiring Al 1 at the base surface of wiring Al 2 becomes small. Thus, this situation serves the purpose of improving the step coverage of wiring Al 2 at the stepped part and accordingly, preventing the disconnection of wiring Al 2 at the stepped part.

7. 发明专利

JPH04362592A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH04362592A
公开(公告)日：1992-12-15
申请号：JP16350991
申请日：1991-06-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI YUKIE , MURANAKA MASAYA , MATSUURA NOBUMI , NAKAGOME YOSHINOBU , TANAKA HITOSHI , YAMAZAKI EIJI , SAKUTA TOSHIYUKI
IPC分类号： G11C11/401 , G11C7/10 , G11C11/409 , G11C29/00 , G11C29/34 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To expand the number of parallel bits in the multi-bit parallel test mode of a dynamic RAM, etc., without being restricted with the number of sub IO line. CONSTITUTION:A memory array is constituted of memory mats from MAT00 L-MAT07L to MAT10R-MAT17R, etc., and a first common data line where a bit line is connected selectively, that is, the sub IO line and a second common data line where the sub IO line is connected selectively, that is, main IO lines group MI0G0-MI0G7 are provided. A main amplifier constituting a main amplifier unit MAU0 and arranged to align in the direction of the prolongation of a word line is provided with a first main amplifier necessitating relatively large operating current and second main amplifier necessitating relatively small operating current, and the main amplifier is chosen according to an operating mode.

8. 发明专利

JPH04181591A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH04181591A
公开(公告)日：1992-06-29
申请号：JP30891590
申请日：1990-11-16
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI YUKIE , MURANAKA MASAYA , MATSUURA NOBUMI
IPC分类号： G11C11/407 , G11C11/401
摘要： PURPOSE:To enable memory capacity to be increased and these to be laid out easily by extending and placing an address decoder for forming word line selection signal and a word line drive circuit in a parallel direction of each bit line. CONSTITUTION:A word driver 2 and a row address decoder 3 are extended and placed by directing them in a parallel direction of each complimentary bit lines DL0, DO0* (* indicates inversion or row enable) - DLn, DLn* and a unit circuit of the decoder 3 and the driver 2 can be placed matching pitch of a complimentary pitch line where the pitch is larger than that of word lines WL1 - WLm, thus enabling the driver 2 and the decoder 3 to be placed easily even if the wiring pitch is small accompanied by increase in memory capacity and miniaturization of circuit element.

9. 发明专利

JPH04155862A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04155862A
公开(公告)日：1992-05-28
申请号：JP28148590
申请日：1990-10-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MURANAKA MASAYA , II HARUO , SUZUKI YUKIE , MATSUURA NOBUMI , YOSHIKAWA KAZUE , ABE JUNICHI , KOYAMA YOSHIHISA , ARAI KOJI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/10 , H01L27/108
摘要： PURPOSE:To enhance a semiconductor integrated circuit device provided with a complementary MISFET in electrostatic breakdown strength when a high voltage is applied to a well region by a method wherein a third semiconductor region which is of the same conductivity type with a first well region or a first semiconductor region and higher than the first well region in impurity concentration is provided to the primary surface of a semiconductor substrate. CONSTITUTION:An N-type well region 2 and a P-type well region 3 are provided onto the different regions of the primary surface of a P -type semiconductor substrate 1 respectively. The P -type semiconductor substrate 1 is set as low in impurity concentration as 1X10 [atoms/cm ] or so. The N-type well region 2 is made to serve primarily as a region where a P channel MISFET Qp of a complementary MISFET is arranged and set as intermediate in impurity concentration as 2X10 [atoms/cm ] or so. The P-type well region 3 is made to serve as a region where a N channel MISFET Qn of the complementary MISFET is arranged and set as intermediate in impurity concentration as 5X10 [atoms/cm ] or so higher than that of the P -type semiconductor substrate 1.

10. 发明专利

JPH02246147A OUTPUT BUFFER AND PROTECTIVE CIRCUIT; SEMICONDUCTOR STORAGE DEVICE CONTAINING THEM; ITS TYPE DEVELOPMENT, LAYOUT SYSTEM AND TEST SYSTEM 失效
公开(公告)号：JPH02246147A
公开(公告)日：1990-10-01
申请号：JP6583889
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKAHASHI YASUSHI , IWAI HIDETOSHI , OGUCHI SATOSHI , NAKAMURA TAKASHI , UCHIYAMA HIROYUKI , TAKEKUMA SHUNJI , SAKOMURA SHIGETOSHI , MIYAZAWA KAZUYUKI , ISHIHARA MASAMICHI , HORI RYOICHI , KIZAKI TAKESHI , KOYAMA YOSHIHISA , II HARUO , MURANAKA MASAYA , AOYANAGI HIDETOMO , MATSUURA NOBUMI
IPC分类号： G11C11/41 , G11C11/34 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/12 , H01L21/60 , H01L21/66 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/50 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To efficiently develop types of a semiconductor storage device by a method wherein a common semiconductor substrate provided with the following is prepared and is owned jointly by a plurality of package specifications: a plurality of bonding pads arranged in optimum positions according to individual package shapes; a bonding pad, for control, which makes selectively effective a plurality of buffers corresponding to the pads and the plurality of bonding pads. CONSTITUTION:On a common semiconductor substrate of a dynamic RAM, names of pads used in the dynamic RAM according to DIP and SOJ package specifications are mentioned at the inside of a dotted line; names of pads used in the dynamic RAM according to ZIP package specifications are mentioned at its outside. This dynamic RAM is classified into a total of 21 product types according to its bit constitution, its operating mode and its package shape. Accordingly, when a semiconductor substrate which is common to all of the 21 product types is prepared and one part of its photomask is changed or a bonding treatment is executed selectively on a prescribed pad, either of the product types can be realized in a alternative way.

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