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1. 发明专利

JPH07202017A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH07202017A
公开(公告)日：1995-08-04
申请号：JP33651993
申请日：1993-12-28
申请人： HITACHI LTD , HITACHI INSTRUMENTS ENG , HITACHI HOKKAI SEMICONDUCTOR , HITACHI VLSI ENG
发明人： UCHIYAMA HIROYUKI , KANEKO YOSHIYUKI , SOEDA KOKI , FUJIOKA YASUHIDE , MATSUDA NOZOMI , SAWAMURA MOTOKO
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To improve the level of integration of a device provided with a memory cell constituted of a series circuit of an MISFET for selecting memory cells and a capacitance element for storing data, by constituting the capacitance element on the gate electrode of the MISFET. CONSTITUTION:A memory cell M is constituted of an MISFET Q for selecting memory cells and a capacitance element C for storing data. A plurality of the memory cells are arranged in the row direction where word lines WL stretch and in the column direction where data lines DL stretch, and a memory cell array is constituted. One side semiconductor region 10 of the MISFET Q for selecting memory cells is connected with the data lines DL, and the other semiconductor region 10 is connected with the one side electrode (storage electrode 8A) of the capacitance element C for storing data. A gate electrode 4A is connected with the word lines WL. The other electrode (a common plate electrode 6A) is connected with a fixed potential, e.g. 1/2 Vcc fixed potential, and the level of integration of a semiconductor integrated circuit device can be increased.

2. 发明专利

JPH02246149A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR REMEDYING DEFECT THEREOF 失效
公开(公告)号：JPH02246149A
公开(公告)日：1990-10-01
申请号：JP6583989
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI DEVICE ENG
发明人： SAKUTA TOSHIYUKI , ISHIHARA MASAMICHI , MIYAZAWA KAZUYUKI , HIROKI MASANORI , IWAI HIDETOSHI , NAKAMURA TAKASHI , TAKAHASHI YASUSHI , MAEDA TOSHIO , MATSUURA NOBUMI , HORI RYOICHI , SASAKI TOSHIO , SAKAI OSAMU , UCHIYAMA HIROYUKI
IPC分类号： G11C29/00 , G11C11/401 , G11C11/406 , G11C29/04 , H01L21/82 , H01L27/10
摘要： PURPOSE:To simplify and rationalize a layout by a method wherein a circuit having a RAM function is formed as a macrocell and a plurality of macrocells constitute a semiconductor storage circuit of a large storage capacity. CONSTITUTION:In this RAM, a plurality of memory blocks which has been formed as macrocells are arranged in a matrix manner. Sixteen memory blocks of about 4 Mbits each are arranged in four rows and four columns and have a large storage capacity of about 64 Mbits as a whole. One memory block constituted as the macrocell is provided with the following: a row-based address decoder which receives an address signal supplied through a timing/address generation circuit which have been made common; an address selection circuit composed of a word-line drive circuit, a column-based address decoder, a column selection-line drive circuit or the like; a timing generation circuit which generates a time-series timing pulse when an internal operation is required according to a memory array and an operating mode; a timing generation circuit for a selected memory cell; an input/output circuit which executes a write/readout operation of a data for the selected memory cell.

3. 发明专利

JPH08191104A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JPH08191104A
公开(公告)日：1996-07-23
申请号：JP255195
申请日：1995-01-11
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI MICROCOMPUTER SYST
发明人： SUZUKI MASAYASU , NISHIHARA SHINJI , SAWARA MASASHI , ISHIDA SHINICHI , ABE HIROMI , TODA SONOKO , UCHIYAMA HIROYUKI , TSUGANE HIDEAKI , YOSHIURA AIMEI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L23/522
摘要： PURPOSE: To strengthen the bonding between a bonding pad and a wire. CONSTITUTION: An Al wiring 35 as the topmost layer is composed of the compound film of the first barrier metal comprising a laminated film of a Ti film 30 and a TiN film 32 as well as an Al film 33 deposited on the first barrier metal and the second barrier metal composed of another TiN film 34 deposited on the Al film 33 so that the deposition of a reactant of Al and Ti on the surface of a bonding pad may be avoided.

4. 发明专利

JPH088348A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND FABRICATION THEREOF 失效
公开(公告)号：JPH088348A
公开(公告)日：1996-01-12
申请号：JP13707494
申请日：1994-06-20
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR , HITACHI INSTRUMENTS ENG , HITACHI VLSI ENG
发明人： FUJIOKA YASUHIDE , UCHIYAMA HIROYUKI , KANEKO YOSHIYUKI , SOEDA KOKI , MATSUDA NOZOMI , SAWAMURA MOTOKO
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108
摘要： PURPOSE:To enhance reliability of a DRAM, along the fabrication yield thereof, in which capacitive insulating film of a capacitive element (capacitor) for storing information is composed of a ferroelectric trim. CONSTITUTION:A polisilicon film 13 filling a contact hole 12 reaching one semiconductor region 7 of an MTSFET Qt for selecting the memory cell constitutes a storage electrode 13. The surface of the storage electrode 13 is then made flat thus depositing a PZT film 14 with low step coverage stably. Furthermore, the upper and lower layers of the PZT film 14 are provided with high melting point metal films 15, 17 in order to prevent interfacial reaction between the storage electrode or a plate electrode 16 and the PZT film 14 caused by heat treatment during the fabrication process.

5. 发明专利

JPH07321095A PATTERN FORMING METHOD AND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07321095A
公开(公告)日：1995-12-08
申请号：JP11492294
申请日：1994-05-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： UCHIYAMA HIROYUKI , HIRATA KOJI
IPC分类号： H01L29/73 , H01L21/302 , H01L21/3065 , H01L21/331 , H01L21/365 , H01L29/737
摘要： PURPOSE:To suppress groove-like abnormal etching farmed around a mask pattern for constant patterning in a wafer surface by coating the rear surface of semiconductor wafer with a metal or conductive material of sufficient thickness so that the concentration of reactive ion caused by the deviation of surface electric field around the mask is suppressed. CONSTITUTION:A compound semiconductor structure consisting of a emitter cap 12, emitter 13, base 14, collector 15 and sub-collector 16 is, with a tungsten silicide which is an emitter electrode 11 used as a cask, etching processed by the portion from the emitter cap 12 to the emitter 13. During this process, the rear side of wafer is coated with the tungsten silicide 18, for microwave etching. The electrode effect of the emitter electrode 11 is relaxed with the tungsten silicide 18 on the rear side. Thus, constant processing is obtained under significantly good controllability.

6. 发明专利

JPH02246147A OUTPUT BUFFER AND PROTECTIVE CIRCUIT; SEMICONDUCTOR STORAGE DEVICE CONTAINING THEM; ITS TYPE DEVELOPMENT, LAYOUT SYSTEM AND TEST SYSTEM 失效
公开(公告)号：JPH02246147A
公开(公告)日：1990-10-01
申请号：JP6583889
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKAHASHI YASUSHI , IWAI HIDETOSHI , OGUCHI SATOSHI , NAKAMURA TAKASHI , UCHIYAMA HIROYUKI , TAKEKUMA SHUNJI , SAKOMURA SHIGETOSHI , MIYAZAWA KAZUYUKI , ISHIHARA MASAMICHI , HORI RYOICHI , KIZAKI TAKESHI , KOYAMA YOSHIHISA , II HARUO , MURANAKA MASAYA , AOYANAGI HIDETOMO , MATSUURA NOBUMI
IPC分类号： G11C11/41 , G11C11/34 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/12 , H01L21/60 , H01L21/66 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/50 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To efficiently develop types of a semiconductor storage device by a method wherein a common semiconductor substrate provided with the following is prepared and is owned jointly by a plurality of package specifications: a plurality of bonding pads arranged in optimum positions according to individual package shapes; a bonding pad, for control, which makes selectively effective a plurality of buffers corresponding to the pads and the plurality of bonding pads. CONSTITUTION:On a common semiconductor substrate of a dynamic RAM, names of pads used in the dynamic RAM according to DIP and SOJ package specifications are mentioned at the inside of a dotted line; names of pads used in the dynamic RAM according to ZIP package specifications are mentioned at its outside. This dynamic RAM is classified into a total of 21 product types according to its bit constitution, its operating mode and its package shape. Accordingly, when a semiconductor substrate which is common to all of the 21 product types is prepared and one part of its photomask is changed or a bonding treatment is executed selectively on a prescribed pad, either of the product types can be realized in a alternative way.

7. 发明专利

JP2014013851A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014013851A
公开(公告)日：2014-01-23
申请号：JP2012151027
申请日：2012-07-05
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： UCHIYAMA HIROYUKI , WAKANA HIRONORI
IPC分类号： H01L29/786 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide a technology of enabling improvement of performance of a semiconductor device.SOLUTION: A thin film transistor 10 includes a wire member 12 supported on a support substrate 11. The wire member 12 has as a core, a conductor wire 20 which functions as a gate line, and a surface of the conductor wire 20 is sequentially covered with a gate insulation film 21 and a channel layer 22. The wire member 12 is supported in a sandwiched manner by source/drain electrodes 13, 14 formed on the support substrate 11. The source/drain electrodes 13, 14 are electrically connected with the channel layer 22 at positions away from each other along a circumferential direction of a cross section of the wire member 12.
摘要翻译：要解决的问题：提供能够提高半导体器件的性能的技术。解决方案：薄膜晶体管10包括支撑在支撑基板11上的线构件12.线构件12具有作为芯的导线 20，其用作栅极线，并且导体线20的表面依次被栅极绝缘膜21和沟道层22覆盖。线构件12以形成的源极/漏极13,14夹持的方式被支撑源极/漏极13,14沿着线构件12的横截面的圆周方向彼此远离的位置与沟道层22电连接。

8. 发明专利

JP2013125782A Oxide semiconductor device 审中-公开
标题翻译：氧化物半导体器件
公开(公告)号：JP2013125782A
公开(公告)日：2013-06-24
申请号：JP2011272337
申请日：2011-12-13
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： UCHIYAMA HIROYUKI , KAWAMURA TETSUSHI , WAKANA HIRONORI , OZAKI HIROAKI , YAMAZOE TAKANORI
IPC分类号： H01L29/786 , G02F1/1368
摘要： PROBLEM TO BE SOLVED: To provide an oxide semiconductor device having good characteristics and high reliability even when a flexible substrate is used.SOLUTION: An oxide semiconductor device has: a gate electrode 2; a gate insulating layer 3 provided on the gate electrode 2; a channel part provided on the gate electrode 2 via the gate insulating layer 3; and source-drain electrodes 6 electrically connected with the channel part. The channel part includes an oxide semiconductor layer 5 and a conductive layer 4. At least one of the source-drain electrodes 6 is connected to the conductive layer 4 via the oxide semiconductor layer 5.
摘要翻译：要解决的问题：即使使用柔性基板，也提供具有良好特性和高可靠性的氧化物半导体器件。解决方案：氧化物半导体器件具有：栅电极2; 设置在栅极电极2上的栅极绝缘层3; 经由栅极绝缘层3设置在栅极电极2上的沟道部分; 以及与沟道部电连接的源极 - 漏极电极6。沟道部分包括氧化物半导体层5和导电层4.至少一个源 - 漏电极6经由氧化物半导体层5连接到导电层4.版权所有（C）2013，JPO和INPIT

9. 发明专利

JP2010192560A Method of manufacturing field effect transistor having oxide semiconductor 有权
标题翻译：制造具有氧化物半导体的场效应晶体管的方法
公开(公告)号：JP2010192560A
公开(公告)日：2010-09-02
申请号：JP2009033577
申请日：2009-02-17
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： WAKANA HIRONORI , UCHIYAMA HIROYUKI , KAWAMURA TETSUSHI , SAITO SHINICHI
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L21/02631 , H01L21/02554 , H01L21/02565 , H01L29/7869
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a field effect transistor which has high alignment accuracy between a gate electrode and source and drain electrodes and achieves a transparent device inexpensively. SOLUTION: Since a patterned light blocking film 102 is formed on the rear side of a substrate 101 and used as a photomask for forming a pattern of the gate electrode 103 and a pattern of the source and drain electrodes 108 on the front side of the substrate, the number of photomasks is reduced, and self-alignment between the gate electrode and the source and drain electrodes is carried out, thereby improving the alignment accuracy of these electrodes. Thereby, the method of manufacturing the high-accuracy inexpensive field effect transistor can be provided. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种在栅电极和源漏电极之间具有高对准精度的场效应晶体管的制造方法，并且廉价地实现透明器件。解决方案：由于在基板101的背面形成有图案遮光膜102，并且用作用于形成栅电极103的图案的光掩模和前侧的源极和漏电极108的图案，光掩模的数量减少，并且进行栅电极与源漏电极之间的自对准，从而提高这些电极的对准精度。由此，可以提供制造高精度廉价的场效应晶体管的方法。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2010140919A Oxide semiconductor device, manufacturing method thereof, and active matrix substrate 审中-公开
标题翻译：氧化物半导体器件及其制造方法和有源矩阵衬底
公开(公告)号：JP2010140919A
公开(公告)日：2010-06-24
申请号：JP2008312814
申请日：2008-12-09
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： UCHIYAMA HIROYUKI , KAWAMURA TETSUSHI , WAKANA HIRONORI
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02617 , H01L21/28291 , H01L27/10873 , H01L27/112 , H01L27/11206 , H01L27/1225 , H01L27/3262 , H01L51/5206
摘要： PROBLEM TO BE SOLVED: To solve the problem that a characteristic which an oxide semiconductor material originally has cannot be utilized due to a difference in work function and difficulty in reducing contact resistance between a metal electrode material and an oxide semiconductor thin-film transistor such as indium oxide gallium zinc and zinc oxide tin. SOLUTION: A phenomenon is utilized in which contact resistance between a semiconductor oxide and metal varies depending on the percentage of added oxygen in gas which is introduced at the film-formation of the semiconductor oxide such as indium oxide gallium zinc and zinc oxide tin. The contact resistance can be suppressed by raising the percentage of added oxygen to 10% or higher, however, in contrast, a threshold potential shift tends to increase. Therefor, a region from the surface where a metal contacts with the semiconductor oxide down to as deep as at least 3 nm is formed as a contact layer with the percentage of added oxygen being 10% or higher while the region being a main channel layer is formed at the percentage of the added oxygen of 10% or lower to form a multilayer structure. Thus, both an ohmic property relative to an electrode metal and reliability in suppressing the threshold potential shift can be made compatible. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题为了解决由于功函数的不同而难以使金属电极材料与氧化物半导体薄膜之间的接触电阻降低的问题，原来具有氧化物半导体材料的特性不能利用的问题晶体管，如氧化铟镓锌和氧化锌锡。解决方案：利用半导体氧化物和金属之间的接触电阻根据在氧化铟镓锌和氧化锌等半导体氧化物成膜时引入的气体中添加的氧气的百分比而变化的现象锡。可以通过将添加的氧的百分比提高到10％以上来抑制接触电阻，然而，相反，阈值电位偏移趋于增加。因此，形成从金属与半导体氧化物接触至深度至少3nm的表面的区域作为接触层，其中添加的氧的百分比为10％以上，而主沟道层的区域为以加入的氧气的百分比形成10％以下，形成多层结构。因此，相对于电极金属的欧姆特性和抑制阈值电位偏移的可靠性都可以兼容。版权所有（C）2010，JPO＆INPIT

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