专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH02210865A FIELD-EFFECT TRANSISTOR OF E/D CONSTITUTION 失效
公开(公告)号：JPH02210865A
公开(公告)日：1990-08-22
申请号：JP2983989
申请日：1989-02-10
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUCHIGAMI NOBUTAKA , TAKATANI SHINICHIRO
IPC分类号： H01L27/095
摘要： PURPOSE:To make it possible to realize easily a field-effect transistor(FET) of an E/D constitution by a method wherein insulators or semiconductors having a large energy forbidden band width are arranged between a semiconductor layer and a Schottky electrode, which are provided on a semiconductor substrate, in a lattice type. CONSTITUTION:In a Schottky junction between a gate 5 and an active layer 2, lattices 3 are formed of an insulating film and channels in bulk parts under the lattices 3 are opened and shut by depletion layers 8, which are generated by metal-semiconductor junctions in the gaps of the lattices 3, from their sides. By changing the widths of the lattices 3, an adjustment of a threshold voltage is also possible. Moreover, as the layers 8 of a metal semiconductor field-effect transistor (a MESFET) are formed thin on the side of a source of the transistor and are formed thick on the side of a drain of the transistor, the threshold voltage varies by the mask-alignment deviation of the lattices 3 with the gate 5 in a current direction if the lengths of the lattices 3 are shorter than a gate length. Therefore, the lengths of the lattices 3 are made longer than the gate length. Thereby, the method of E/D constitution which is easily applicable even to the MESFET is obtained.

2. 发明专利

JPH033336A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH033336A
公开(公告)日：1991-01-09
申请号：JP13603689
申请日：1989-05-31
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUCHIGAMI NOBUTAKA , TAKATANI SHINICHIRO
IPC分类号： H01L29/812 , H01L21/338
摘要： PURPOSE:To lessen a fluctuation in a threshold voltage due to a voltage from the rear of a semiconductor substrate and to make possible the stable operation of a circuit by a method wherein a high-resistance intermediate layer is provided between the substrate and an operating layer. CONSTITUTION:In a field-effect transistor having an operating layer 5 which is formed on a semiconductor substrate 1 by an epitaxial growth, a high- resistance intermediate layer 2 is provided between the substrate 1 and the layer 5. For example, in a MESFET, which is manufactured by stacking in order a buffer layer 3, a P-type buried layer 4 and an operating layer 5 on a semi-insulative GaAs substrate 1 by an epitaxial growth, an intermediate layer 2 having a deep level is intentionally provided under or on the layer 3. The layer 3 is of an undoped GaAs, the layer 4 is one doped with Be ions, about 3X10 cm , as an acceptor impurity, the layer 5 is one doped with a donor impurity of Si ions, about 2X10 cm , and the layer 2 is a GaAs layer doped with Cr ions, about 5X10 cm .

3. 发明专利

JPH02210840A FIELD-EFFECT TRANSISTOR 失效
公开(公告)号：JPH02210840A
公开(公告)日：1990-08-22
申请号：JP2984089
申请日：1989-02-10
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUCHIGAMI NOBUTAKA , TAKATANI SHINICHIRO
IPC分类号： H01L29/812 , H01L21/338
摘要： PURPOSE:To enable the title FET in which the carrier mobility of an active layer provided with a buried p layer is augmented to be manufactured by inserting an undoped layer between the active layer and the buried p layer. CONSTITUTION:An n layer 6 is formed by ion-implantation while an i-GaAs 3 in specified thickness is held between an active layer 2 and a p layer 4. This is caused by almost specified thickness of a depletion layer extending over the n layer side when the n layer 2 and the p layer 4 are brought into contact with each other. Accordingly, the interface between the active layer 2 and the buried p layer 4 is depleted by a pn junction, however, the impurity concentration in the interface is higher since the interface contains the acceptor in the p layer 4 and the donor in the n layer 2 so as to lower the carrier mobility. Through these procedures, the title FET can be accelerated by forming the interface of an undoped layer in high mobility.

4. 发明专利

JPH07245338A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH07245338A
公开(公告)日：1995-09-19
申请号：JP3330994
申请日：1994-03-03
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KIKAWA TAKESHI , TAKATANI SHINICHIRO , SHIGETA JUNJI , FUCHIGAMI NOBUTAKA
IPC分类号： H01L21/76 , H01L21/265 , H01L27/095
摘要： PURPOSE:To provide a semiconductor device which has a small amount of impurity and levels produced by uncoupled hands and has a high-quality high- resistance layer and its manufacturing method. CONSTITUTION:A high-resistance layer 11 is formed by radiating atomic hydrogen 10 upon the surface of a compound semiconductor substrate 12 and diffusing the hydrogen into the semiconductor from the surface. When the dose of the atomic hydrogen 10 is controlled, the resistance of the layer 11 can be adjusted to a desired value. Therefore, when the hydrogen 10 is supplied to the surface of the substrate 12, the diffusion of the hydrogen into the semiconductor is accelerated. In addition, since the hydrogen introduced into the semiconductor is coupled with other impurities and uncoupled hands and makes levels caused by these point defects inactive, a high-quality high-resistance layer containing a small amount of levels can be obtained. Therefore, not only the high-frequency characteristics, isolation between elements in integrated circuits, etc., can be improved, but also an equivalent circuit having a prescribed resistance value can easily be obtained by controlling the load resistance in a resistance element.

5. 发明专利

JPH076974A MANUFACTURE OF COMPOUND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH076974A
公开(公告)日：1995-01-10
申请号：JP14593693
申请日：1993-06-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUCHIGAMI NOBUTAKA , TAKATANI SHINICHIRO
IPC分类号： C23C14/06 , H01L21/22
摘要： PURPOSE:To enable a compound semiconductor device to be lessened in thermal treatment temperature and make a diffusion source film prescribed in thickness and quality with high reproducibility by a method wherein a high melting point metal silicide prescribed in Si composition is formed on a compound semiconductor layer, a nitride film is deposited thereon, and then Si is diffused by thermal treatment. CONSTITUTION:A WSix film 2 (x>0.8) is deposited on an undoped or a P-type GaAs layer 4 as thick as 30mm or below through a magnetron sputtering method, and the WSix film 2 is partially removed leaving a part where a conductive layer is formed unremoved. Thereafter, a W5Si3 target is sputtered in an atmosphere of nitrogen for depositing a WSixNy film 1. The wafer composed of the films 4, 2, and 1 is thermally treated to diffuse Si contained in the WSix film 2 to form an N-type conductive layer 8. After the WSixNy film 1 and the WSix film 2 are removed, a recess as deep as 20mm or so is so provided by etching to a gate forming region as to remove the influence of diffused W, and a gate electrode 3 is provided. The gate electrode 3 is formed through such a manner that a W5Si3 target is sputtered in a vacuum under conditions so controlled as to enable the electrode 3 to be of WSi0.4 in composition.

6. 发明专利

JPH02142179A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02142179A
公开(公告)日：1990-05-31
申请号：JP29457588
申请日：1988-11-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUCHIGAMI NOBUTAKA , TAKATANI SHINICHIRO
IPC分类号： H01L29/73 , H01L21/331 , H01L27/095 , H01L29/205 , H01L29/737
摘要： PURPOSE:To decrease a collector junction capacitance on the side of an HBT, to decrease a parasitic capacitance beneath a channel on the side of a FET and to make it possible to perform high speed operation by fixing the potential of a P layer on the side of the FET, and using the upper part of the P layer as a non-doped layer. CONSTITUTION:An electrode 15 is provided for a P layer, and a potential is fixed. A part to a non-doped layer 5 is formed at first by crystal growing. Thereafter, the side of a FET and the side of an HBT are separated. After a channel 7 is formed on the FET side, a gate electrode 12 is formed. An N layer 6 is formed by selective epitaxial growing. At this time, the growing step of the N layer 6 and the annealing step of the channel 7 and an N' layer 8 can be performed as one step. Finally, electrodes 9, 10, 11, 12, 13 and 15 are formed at the same time, and a wiring step is performed. Thus an integrated circuit is formed.

7. 发明专利

JPH02199843A COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH02199843A
公开(公告)日：1990-08-08
申请号：JP1765589
申请日：1989-01-30
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ODA HIROTO , TAKATANI SHINICHIRO , MIYAZAKI MASARU , SHIGETA JUNJI
IPC分类号： H01L29/812 , H01L21/338
摘要： PURPOSE:To form sidewalls of a silicon nitride film with good reproducibility by a method wherein the silicon nitride film is etched by making use of sidewalls of a silicon oxide film as a mask. CONSTITUTION:An n-type active channel region 21 is formed on a GaAs substrate crystal 1; a gate electrode 3 and a silicon nitride film 5 are formed on them; a photoresist 71 as a mask material having opening parts in parts corresponding to active channels is formed. Then, Si ions are implanted by making use of the gate electrode 3 as a mask. Then, the photoresist 71 is removed; after that, a silicon oxide film 61 is formed on the silicon nitride film 5; the silicon oxide film 61 is etched selectively and removed by making use of the photoresist 72 as a mask; sidewalls 8 of the silicon oxide film are left on side faces of the gate electrode 3. Then, the exposed silicon nitride film 5 is etched selectively and removed by making use of the sidewalls 8 of the silicon oxide film as a mask; the n ion implantation layer 4 is exposed.

8. 发明专利

JP2008004807A Heterojunction bipolar transistor 审中-公开
标题翻译：异相双极晶体管
公开(公告)号：JP2008004807A
公开(公告)日：2008-01-10
申请号：JP2006173730
申请日：2006-06-23
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MOCHIZUKI KAZUHIRO , MATSUMOTO HIDETOSHI , TAKATANI SHINICHIRO
IPC分类号： H01L21/331 , H01L29/73 , H01L29/737
CPC分类号： H01L29/66318 , H01L27/0605 , H01L29/2003 , H01L29/737
摘要： PROBLEM TO BE SOLVED: To provide a heterojunction bipolar transistor which secures a base collector breakdown voltage and a current amplifying rate while being reduced in a base resistance.
SOLUTION: The heterojunction bipolar transistor has on the surface of the substrate sequentially in a parallel direction an emitter contact region, an emitter region consisting of a first semiconductor material, a base region consisting of a second semiconductor having a forbidden band width smaller than that of the first semiconductor material, a collector region consisting of the first semiconductor material, and a collector contact region. In this case, a buffer layer consisting of a third semiconductor material having the forbidden band width larger than that of the first semiconductor material is provided between the emitter region, base region as well as the collector region and the surface of the substrate while an emitter electrode, a base electrode, and a collector electrode are formed so as to be contacted with the emitter contact region, the base region, and the collector region.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种在基极电阻降低的同时确保集电极击穿电压和电流放大率的异质结双极晶体管。解决方案：异质结双极晶体管在平行方向上顺序地在发射极接触区域，由第一半导体材料组成的发射极区域，由禁带宽度较小的第二半导体构成的基极区域与第一半导体材料相比，由第一半导体材料和集电极接触区域组成的集电极区域。在这种情况下，在发射极区域，基极区域以及集电极区域和衬底的表面之间设置由具有大于第一半导体材料的禁带宽度的第三半导体材料构成的缓冲层，而发射极电极，基极电极和集电极形成为与发射极接触区域，基极区域和集电极区域接触。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2003258003A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2003258003A
公开(公告)日：2003-09-12
申请号：JP2002059905
申请日：2002-03-06
申请人： HITACHI LTD
发明人： TAKAZAWA HIROYUKI , TAKATANI SHINICHIRO , YAMANE MASAO , KOBAYASHI MASAYOSHI
IPC分类号： H01L29/812 , H01L21/335 , H01L21/338 , H01L29/06 , H01L29/778 , H01L31/0328 , H01L31/0336 , H01L31/072
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for use at high frequencies which exhibits a high dielectric breakdown voltage, and to provide its manufacturing method. SOLUTION: A region 11 including a heavily-doped semiconductor of a first conductivity-type and a region 12 including a lightly-doped semiconductor of a first conductivity-type are provided on the side of a barrier layer 5 farther away from a semiconductor substrate 1 than its end opposite to the semiconductor substrate 1 and between an ohmic layer 7 and a gate electrode 10. The sheet impurity concentration of the region 12 is set lower than the sheet impurity concentration between the bottom face of the gate electrode 10 on the side of the semiconductor substrate 1 and the end face of a channel layer 3 opposite to the semiconductor substrate 1. Additionally, the sheet impurity concentration of the region 11 is set higher than the sheet impurity concentration of the region 12. Consequently, a semiconductor device exhibiting a high dielectric voltage for use at high frequencies can be obtained. COPYRIGHT: (C)2003,JPO

10. 发明专利

JP2001077128A HIGH FREQUENCY MODULE 失效
公开(公告)号：JP2001077128A
公开(公告)日：2001-03-23
申请号：JP25247099
申请日：1999-09-07
申请人： HITACHI LTD
发明人： TAKATANI SHINICHIRO , TANIMOTO TAKUMA , HIGUCHI KATSUHIKO , UCHIYAMA HIROYUKI
IPC分类号： H01L23/12 , H01L21/338 , H01L29/778 , H01L29/80 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a high frequency module in millimeter wave band having excellent high-frequency characteristics where an MMIC(monolithic microwave integrated circuit) is mounted to improve the S/N ratio and reduce the source inductance. SOLUTION: As a basic element of an MMIC constituting a high frequency module, a distortion-relaxed HEMT(high electron mobility transistor) is used, where the substrate under an element region 3 is removed to expose a distortion- relaxed layer 2 in which fluorine is diffused with a rear-surface electrode 8 directly contacting it, while a minute via hole 7 is provided directly under a source electrode 4 for reduced source inductance. Thus, fluctuations in characteristics of element and low frequency noise due to carrier traps or charging/discharging, etc., at the defect level of the distortion-relaxed layer are suppressed, so that the S/N of MMIC is improved for a high frequency module and satisfactory high frequency characteristics are obtained.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式