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1. 发明专利

JP2002150785A NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2002150785A
公开(公告)日：2002-05-24
申请号：JP2000345455
申请日：2000-11-08
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MATSUZAKI NOZOMI , SHIBA KAZUYOSHI , TANIGUCHI YASUHIRO , TANAKA TOSHIHIRO , SHINAGAWA YUTAKA
IPC分类号： G11C16/06 , G11C8/08 , G11C16/02 , G11C16/12 , G11C16/34
摘要： PROBLEM TO BE SOLVED: To improve convergency and to perform high speed erasure in erasure operation of a non-volatile semiconductor memory. SOLUTION: A word latch circuit is provided for each word line, and threshold value control is performed for each word line in a selection block. The latch circuit shares plural word lines, and occupancy area is reduced. Rewriting voltage is set individually to a completed non-volatile memory, stored in a boot region of the non-volatile memory, and recognizing anew is performed for each a supplying of a power source.

2. 发明专利

JPH08250614A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH08250614A
公开(公告)日：1996-09-27
申请号：JP5220195
申请日：1995-03-13
申请人： HITACHI LTD
发明人： MATSUZAKI NOZOMI , FUKAMI AKIRA , YAHATA HIDEJI , NAGANO TAKAHIRO
IPC分类号： H01L21/28 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06
摘要： PURPOSE: To provide a semiconductor device contains a microminiature semiconductor element having favorable electrical characteristics. CONSTITUTION: The gate electrodes of a complementary MOS transistor are formed on a semiconductor substrate, and are doped with impurities of the same conductivity type. A silicide layer 130 is formed thereon, and a source region of a first conductivity type and a drain region of a second conductivity type are formed on the semiconductor substrate. Silicide layers 130 that are aligned by themselves with the gate electrode, respectively, are formed on the source region and the drain region.

3. 发明专利

JPH0778882A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0778882A
公开(公告)日：1995-03-20
申请号：JP22308593
申请日：1993-09-08
申请人： HITACHI LTD
发明人： MATSUZAKI NOZOMI , FUKAMI AKIRA , NAGANO TAKAHIRO , YAMANAKA TOSHIAKI , YAHATA HIDEJI
IPC分类号： H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092
摘要： PURPOSE:To reduce an apparel parasitic resistance by a method wherein punch- through preventive ion layers having a concentration higher than that of a substrate part are provided directly under source and drain regions in the surface of the substrate and a metal-silicon alloy layer is provided on the respective surfaces of the polysilicon film of source and drain electrodes and the polysilicon film of a gate electrode. CONSTITUTION:A gate oxide film 105 is formed and thereafter, a first polysilicon film 106 is deposited. A second polysilicon film is deposited thereon and an N-type region 109 and a P-type region 110 are formed. After sidewall spacers 121 are formed, high-concentration source and drain regions 122 of an N-MOS transistor and punch-through stopper layers 123 are formed by ion- implantation and moreover, high-concentration source and drain regions 124 of a P-MOS transistor and punch-through stopper layers 125 are formed in the same manner. Moreover, the whole surface is formed into a silicified alloy layer and after an interlayer insulating film 128 is deposited, even metal wirings 127 to 130 are wired. Accordingly, the generation of a parasitic capacitance can be inhibited.

4. 发明专利

JP2003338560A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2003338560A
公开(公告)日：2003-11-28
申请号：JP2003102835
申请日：2003-04-07
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MATSUZAKI NOZOMI , MIZUNO HIROYUKI , HORIGUCHI SHINJI
IPC分类号： H01L21/8234 , H01L21/8242 , H01L21/8244 , H01L21/8246 , H01L27/088 , H01L27/10 , H01L27/108 , H01L27/11 , H01L27/112 , H03K19/00 , H03K19/0948
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device by which a plurality of MOS transistors of different gate insulating film thicknesses are formed on the same substrate. SOLUTION: This method of manufacturing a semiconductor device is for forming a first MOS transistor and a second transistor on the same substrate, wherein the gate insulation film thickness of the first MOS transistor is larger than that of the second MOS transistor. A first layer 105 and a second layer 106, which are oxide-film layers, for forming a gate insulating film and a gate electrode of the first MOS transistor, respectively, are formed and shaped to form the gate insulating film and the gate electrode of the first MOS transistor, respectively. The first layer and the second layer, other than the gate insulating film and the gate electrode of the formed first MOS transistor, are removed. A third layer 111 and a fourth layer 112 for forming the gate insulating film and the gate electrode of the second MOS transistor, respectively, are formed and shaped to form the gate insulating film and the gate electrode of the second MOS transistor, respectively. COPYRIGHT: (C)2004,JPO
摘要翻译：解决的问题：提供一种制造半导体器件的方法，通过该方法，在同一衬底上形成有多个不同栅极绝缘膜厚度的MOS晶体管。解决方案：制造半导体器件的方法是在同一衬底上形成第一MOS晶体管和第二晶体管，其中第一MOS晶体管的栅极绝缘膜厚度大于第二MOS晶体管的栅极绝缘膜厚度。分别形成用于形成第一MOS晶体管的栅极绝缘膜和栅电极的作为氧化物膜层的第一层105和第二层106，形成并形成栅极绝缘膜和栅电极第一个MOS晶体管。除了形成的第一MOS晶体管的栅极绝缘膜和栅电极之外的第一层和第二层被去除。分别形成用于形成栅极绝缘膜和第二MOS晶体管的栅电极的第三层111和第四层112，并且成形为分别形成第二MOS晶体管的栅极绝缘膜和栅电极。版权所有（C）2004，JPO

5. 发明专利

JPH11260063A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH11260063A
公开(公告)日：1999-09-24
申请号：JP5771498
申请日：1998-03-10
申请人： HITACHI LTD
发明人： MIZUNO HIROYUKI , MATSUZAKI NOZOMI , ISHIBASHI KOICHIRO
IPC分类号： G11C11/412
摘要： PROBLEM TO BE SOLVED: To enable high speed operation at a low voltage by respectively connecting a couple of leak elements in a memory cell to a pair of bit lines to make equal currents flowing to a couple of bit lines during non-operation of the memory cell. SOLUTION: A leakage current I4 flows between a bit line BLB and a memory node N2 and a leakage current I3 flows between a bit line BL and a memory node N1. Second transfer MOSFETs NM5 and MN6 are sufficient when these elements allow the identical leakage currents to flow into the memory cell from the bit lines BL and BLB when the word line is set to 0V in the non-selection condition. Since the device characteristics of the second transfer MOSFETs MN5 and MN6 are identical to those of the transfer MOSFET MN3 and MN4, the results, I1=I4 and I2=I3 can be attained. Since a current flowing to the memory cell from the bit line BL is I2+I4 (=I1+I3), the currents flowing into the memory cell from the bit lines BL, BLB become identical and normal mode noise is never generated.

6. 发明专利

JPH0897297A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0897297A
公开(公告)日：1996-04-12
申请号：JP23182294
申请日：1994-09-27
申请人： HITACHI LTD
发明人： TAKASUGI KOICHI , MINAMI MASATAKA , YAMANAKA TOSHIAKI , MATSUZAKI NOZOMI , YAHATA HIDEJI , NAGANO TAKAHIRO
IPC分类号： H01L27/11 , H01L21/8244
摘要： PURPOSE: To reduce the occupation area of a memory cell M so as to improve the integration of a semiconductor integrated circuit device in the semiconductor integrated circuit device having a memory cell M. CONSTITUTION: In a semiconductor integrated circuit device having a memory cell, a gate wiring 6 that is united respectively to a gate electrode 6A for a loading MISFET Qp2 and a gate electrode 6B for a driving MISFET Qd2 through a wiring 12A formed in a connecting hole 11A is electrically connected with a first impurity area 9A as a drain area for the loading MISFET Qp1 and a second impurity area 8A as an impurity area for one of the drain area for the loading MISFET Qd1 and the transfer MISFET Qt1.

7. 发明专利

JPH07307310A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07307310A
公开(公告)日：1995-11-21
申请号：JP9861094
申请日：1994-05-12
申请人： HITACHI LTD
发明人： NAKAMURA YOSHITAKA , KOBAYASHI NOBUYOSHI , HONMA YOSHIO , YAHATA HIDEJI , MATSUZAKI NOZOMI , NAGANO TAKAHIRO
IPC分类号： H01L21/285 , H01L21/265 , H01L21/28 , H01L21/308 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/78
摘要： PURPOSE:To stably form a metal silicide film on a gate electrode region or the like, by a method wherein, after a polycrystalline silicon deposition film is formed on the substrate surface containing a silicide film, heat treatment is performed, and unreacted polycrystalline silicon is selectively eliminated by wet-etching using etching solution whose main component is hydrazine. CONSTITUTION:A titanium silicide film 8 is formed on the surfaces of a gate electrode region 4 and a source/drain region 5. A deposition film 9 composed of polycrystalline silicon is formed on the whole surface of a substrate 1 containing the titanium silicide film 8. By performing heat treatment, reaction is generated between the polycrystalline silicon film 9 and the metal silicide film 8, which is subjected to phase inversion to low resistance composition. Further after the heat treatment, wet etching is performed by using etching solution whose main component is hydrazine, and unreacted polycrystalline silicon is eliminated. Hence only the polycrystalline silicon film 9 is completely eliminated without etching the titanium silicide film 8.

8. 发明专利

JPH04142115A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04142115A
公开(公告)日：1992-05-15
申请号：JP26539290
申请日：1990-10-02
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： MINAMI MASATAKA , WATANABE TOKUO , MATSUZAKI NOZOMI , SHIODA MASASHI , MATSUKI HIROSHI , YOSHIZUMI KEIICHI
IPC分类号： H03K19/08
摘要： PURPOSE:To reduce power consumption by applying a bias voltage to the base of a bipolar transistor different when the bipolar transistor is switched from an off-state to an on-state and when it is switched from the on-state to the off-state. CONSTITUTION:When an input voltage is set at a low level and an output level at a high level, a source voltage Vcc is applied to the base of the bipolar transistor 111 when a FET 107 is turned on and the transistor 111 is turned on, then, an electric charge is charged. At this time, the FET 107 is turned off and FETs 108, 109 are turned on when input is switched to the high level by applying a ground voltage to the source terminal S1 of the FET 108 and the bias voltage V to the source terminal S2 of a FET 110. At this time, the ground voltage is applied to the base of the transistor 111, and potential difference is increased compared with the case when the bias voltage is always applied to the source terminal, which enables a base charge to be extracted faster than ever. Thereby, a through current can be suppressed when an output voltage rises, which realizes low power consumption and acceleration.

9. 发明专利

JP2003218212A SEMICONDUCTOR DEVICE 有权
公开(公告)号：JP2003218212A
公开(公告)日：2003-07-31
申请号：JP2002016466
申请日：2002-01-25
申请人： HITACHI LTD
发明人： KAWAHARA TAKAYUKI , MATSUZAKI NOZOMI , SAWASE TERUMI , KUBO SEIJI
IPC分类号： G11C16/04 , G06F15/78 , H01L21/28 , H01L21/82 , H01L21/8238 , H01L21/8247 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H03K19/173
摘要： PROBLEM TO BE SOLVED: To increase a speed at a low voltage operation in a semiconductor device on which a non-volatile memory unit and a variable logic unit are mounted. SOLUTION: The semiconductor device has a non-volatile memory unit (8) having a rewritable non-volatile memory cell, and a variable logic unit (3) of which the logic function can be decided in accordance with logical configuration definition data loaded into a plurality of memory cells. The non-volatile memory cell has characteristics in which the gate dielectric strength of a select MOS transistor is lowered below that of a memory MOS transistor, or the gate insulating film of the select MOS transistor is thinner in width than that of a high voltage MOS transistor (a fourth MOS transistor) based on a split gate structure constructed with the select MOS transistor (a second MOS type transistor) and the memory MOS transistor (a first MOS type transistor). The select MOS transistor Gm can be increased in performance and a read current can sufficiently be obtained. COPYRIGHT: (C)2003,JPO

10. 发明专利

JP2000138372A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JP2000138372A
公开(公告)日：2000-05-16
申请号：JP31161298
申请日：1998-11-02
申请人： HITACHI LTD
发明人： MATSUZAKI NOZOMI , KOBAYASHI TAKASHI , KUME HITOSHI , MINE TOSHIYUKI , KUSUKAWA KIKUO , SUZUKI NORIO , TAKAHASHI KENJI , NISHIMOTO TOSHIAKI , KATO MASATAKA
IPC分类号： H01L21/76 , H01L27/105 , H01L27/108 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To ensure a withstand voltage necessary for gate oxide films of different levels of thickness by providing a specific relationship of size between a radius of curvature on the side of a groove device separation construction end substrate which is in contact with a gate oxide film of a certain thickness and a radius of curvature on the side of the groove device separation construction end substrate in contact with a gate oxide film of different thickness. SOLUTION: A radius of curvature in the corner on the side of a substrate at the end of a shallow groove where a shallow device separation area provided on a silicon substrate SUB11 and a gate insulating film HOX1 are in contact is named R. Also, the radius of curvature in the corner on the side of the substrate at the end of a shallow device separation area where a shallow groove device separation area provided on a silicon substrate SUB12 and a gate oxide film LOX1 are in contact is named r. In this case, when HOX1>=LOX1, the construction is formed to establish the relationship R>=r. In this way, even when plural levels of gate oxide film thickness are provided, withstand voltage necessary for each of the gate oxide films HOX1 and LOX1 can be ensured.

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