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1. 发明专利

JP2007042655A Ion injection method and its device 有权
标题翻译：离子注射方法及其装置
公开(公告)号：JP2007042655A
公开(公告)日：2007-02-15
申请号：JP2006222881
申请日：2006-08-18
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： UMEMURA KAORU , KAWANAMI YOSHIMI , KATO MASATAKA , MADOKORO YUICHI , KURODA KATSUHIRO , HAYATA YASUNARI
IPC分类号： H01J37/317 , H01L21/265 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide an ion injection method which does not require a resist application process before and after the ion injection process and can reduce the number of manufacturing processes of a semiconductor device. SOLUTION: In the ion injection method, ions emitted from an ion source is made to pass through a mask having nearly similar apertures to the desired ion injection region, and pattern ion beams are formed; and these ion beams are projected on the desired region of wafer on which the resist is not coated, and the ions are introduced. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种离子注入方法，其在离子注入过程之前和之后不需要抗蚀剂施加工艺，并且可以减少半导体器件的制造工艺的数量。解决方案：在离子注入方法中，使离子源发射的离子通过具有与所需离子注入区域几乎相似孔径的掩模，形成图案离子束; 并且将这些离子束投影到其上未涂覆抗蚀剂的晶片的期望区域上，并且引入离子。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2001332967A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2001332967A
公开(公告)日：2001-11-30
申请号：JP2000149174
申请日：2000-05-22
申请人： HITACHI LTD
发明人： MITSUMOTO KINYA , KATO MASATAKA
IPC分类号： G11C11/413 , G11C11/417 , H03K5/08 , H03K19/0175
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device, equipped with an input circuit by which the amplitude of an output signal, is stabilized even at a low voltage. SOLUTION: This device is provided with a resistance means for forming an operating current in the differential form of a first transistor, through which an input signal is supplied to a control input terminal, and a second transistor through which a reference voltage is supplied to a control input terminal, and a variable resistance means through which the voltage of the output node of the first or second transistor is supplied to a control terminal and which is connected serially to the resistance means. Then, the resistance of the variable resistance means at the time of turning on the first transistor is set relatively large, in comparison with the resistance of the variable resistor means at the time of turning on the second transistor, and change of the current to flow to the resistance means is reduced in comparison to change of the input signal. Thus, an output signal amplitude and a DC level are made almost equal to the change of the input signal.

3. 发明专利

JP2000215684A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2000215684A
公开(公告)日：2000-08-04
申请号：JP2000050237
申请日：2000-02-25
申请人： HITACHI LTD
发明人： TANAKA TOSHIHIRO , KATO MASATAKA , SASAKI TOSHIO , KUME HITOSHI , KOTANI HIROAKI , FURUSAWA KAZUNORI
IPC分类号： G11C16/06
摘要： PROBLEM TO BE SOLVED: To perform electrical rewriting of sector information easily while disconnecting a bus between a semiconductor device and a system to be used by detecting the write state of a memory cell related to write operation or write verify operation and controlling continuation/stop of a write operation repeated during a rewrite operation based on the detection results. SOLUTION: If the information of data latch in a sense amplifier circuit SAC specifies at least one write operation after a memory cell state detecting operation is detected by a memory cell state detecting circuit ALLC, write operation is repeated again. If the information of data latch in the sense amplifier circuit SAC entirely represents write non-select state as a result of memory cell state detecting operation, repeated write operations are ended after the memory cell state detecting operation. More specifically, the memory cell state detecting circuit ALLC provided for each data line controls continuation/stop of write operation being repeated during a rewrite operation.

4. 发明专利

JP2000124315A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000124315A
公开(公告)日：2000-04-28
申请号：JP29069198
申请日：1998-10-13
申请人： HITACHI LTD
发明人： KATO MASATAKA
IPC分类号： H01L21/82
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit device that can save a nonconforming product and changed into a conforming one. SOLUTION: A semiconductor integrated circuit device is a logic rewritable programmable LSI consisting of an FPGA(field programmable gate array) and is constituted of a plurality of control logic blocks CLB, a plurality of I/O blocks I/O, and a wiring region LA for connecting the control logic and the I/O blocks. In the wiring region LA, a MOS transistor is provided for the MOS transistor logically to connect the control logic block CLB and to logically disconnect the control logic block CLB of a nonconforming part based on the classification of a nonconforming pattern estimated in advance. When the nonconforming part exists at a part as in the case where the nonconforming part exists in a those odd rows, the MOS transistor is turned off, and the odd column, odd row, even column, even row, or the surface of the control logic block CLB arranged in a lattice shape in addition to the control logic block CLB of the nonconforming part is disconnected, so as to the control logic block CLB of the nonconforming part from being seen from the outside.

5. 发明专利

JPH10241381A NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH10241381A
公开(公告)日：1998-09-11
申请号：JP4673098
申请日：1998-02-27
申请人： HITACHI LTD
发明人： TANAKA TOSHIHIRO , KATO MASATAKA , ADACHI TETSUO
IPC分类号： G11C16/02
摘要： PROBLEM TO BE SOLVED: To suppress distribution of threshold voltages of memory cells and to diminish a difference between writing and erasing threshold voltages so as to enhance the number of rewriting times by rewriting a rewritten data posterior to its rewriting operation and after its verification and performing rewriting operation with this data. SOLUTION: Plural nonvolatile semiconductor memory cells are connected with their control gates in common to word lines W1-Wm, and are connected with their drains in common to bit lines B1 and B2 and also with sources in common to a source line respectively. When writing operation is performed on these memory cells, only insufficient written memory cells are controlled to be continued to be written. Then, when erasing operation is performed on these memory cells, only insufficient erased memory cells are controlled to be continued to be erased. Consequently, distribution of the threshold voltages of the memory cells corresponding to two bits of stored information is suppressed to enhance their rewriting bearability.

6. 发明专利

JPH10233677A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH10233677A
公开(公告)日：1998-09-02
申请号：JP28198997
申请日：1997-10-15
申请人： HITACHI LTD
发明人： OBAYASHI MASAYUKI , KATO MASATAKA , TANBA NOBUO
IPC分类号： H01L21/82 , H03K19/177
摘要： PROBLEM TO BE SOLVED: To provide a field programmable gate array FPGA in which one defective variable logic block is relieved by one standby variable logic block. SOLUTION: The integrated circuit is provided with a standby variable logic block 18 which substitutes a variable logic block 27 whose logic function is variably set. A connection relation between the variable logic block and a regular signal wiring 23 is set variably to variable connection sections 20, 21 provided to the variable logic block 27 and the connection between the regular signal wiring and the variable logic block is replaced with the connection between the regular signal wiring and the standby variable logic block. Thus, one defective variable logic block is replaced with the one standby variable logic block.

7. 发明专利

JPH10107164A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH10107164A
公开(公告)日：1998-04-24
申请号：JP25818896
申请日：1996-09-30
申请人： HITACHI LTD
发明人： OKAZAKI TSUTOMU , KATO MASATAKA , IKEDA YOSHIHIRO , ADACHI TETSUO , TSUCHIYA OSAMU
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To microminiaturize a nonvolatile memory element and to enhance the integration degree of a flash memory by a method wherein, when a thermal-oxidation insulating film is formed, the rolling-up, of a sidewall insulating film, which is generated owing to the growth of the thermal-oxidation insulating film, is eliminated. SOLUTION: A field insulating film 2 which prescribes the length in the gate length direction of an active region on the main face of a p-type semiconductor substrate 1 is formed in a nonactive region on the main face of the p-type semiconductor substrate, and a gate insulating film 3 is formed in the active region on the main face of the p-type semiconductor substrate 1. A gate material 4 which is formed of a polycrystal silicon film, whose surface at the upper part is covered with an oxidation preventive film and whose length in the gate length direction of the gate insulating film 3 is regulated is formed on the surface in the center in the gate length direction. Sidewall insulating films 5B which are formed along the thickness direction of the gate material 4 and which are formed of a silicon nitride film are formed on surfaces of two sidewall faces which are faced with each other in the gate length direction of the gate material 4. One pair of thermally oxidized insulating films 10 are formed between the field insulating film 2 and sidewall spacers 8.

8. 发明专利

JPH1054866A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH1054866A
公开(公告)日：1998-02-24
申请号：JP21071296
申请日：1996-08-09
申请人： HITACHI LTD
发明人： KAZAMA HIDEO , KATO MASATAKA , ISHII SHUICHI , IRIKURA SHINOBU
IPC分类号： G01R31/28 , G06F1/10 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To easily measure the delay of a clock path containing a latch in a short time by measuring a clock signal inputted to a latch by measuring the frequency of the signal. SOLUTION: A tester is connected to a semiconductor integrated circuit device 1 and a selector 6 is switched to select a signal outputted from a clock selector 4 by outputting a select signal. An inverted signal is inputted to one input section of the latch 2 and a signal synchronized to a pulse generating circuit 5 is outputted form the latch 2. Since the output of the latch 2 becomes the inverted signal of the clock signal inputted to one input section of the clock selector 4, a path containing the latch 2 is made to operate as a ring oscillator. Since the frequency of the clock signal can be measured from the output of the latch 2, namely, with the tester connected to the other output section of a distribution circuit 3, the delay of the path containing the latch 2 can be measured. Therefore, the delay of the path can be measured easily in a short time without measuring the waveform of the clock signal.

9. 发明专利

JPH07273231A MANUFACTURE OF NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH07273231A
公开(公告)日：1995-10-20
申请号：JP6238694
申请日：1994-03-31
申请人： HITACHI LTD
发明人： KATO MASATAKA , ADACHI TETSUO , KUME HITOSHI , YADORI SHOJI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To prevent a non-volatile semiconductor memory device from deteriorating in electron injection and discharge characteristic between a floating gate and a channel by a method wherein the upside and side face of a polysilicon layer over a gate insulating film are covered with an insulating film such as a nitride film or an oxide film while an element isolating insulating film is formed. CONSTITUTION:A gate oxide film 12 and a first polysilicon layer 13 are formed on the surface of a P-type semiconductor substrate 1, and a first insulating film composed of a deposit oxide film 14 and a nitride film 15 is formed. These layers are patterned into stripe-like lines in row, and second insulating films 16 and 17 are formed on the side walls of the lines in row. An element isolating insulating film 18 is formed on a surface of the P-type semiconductor substrate 1 which is not covered with the first insulating films 14 and 15 and the second insulating films 16 and 17. A second polysilicon layer 22 is deposited, and the second polysilicon layer 22 and the first polysilicon layer 13 are patterned into lines in column vertical to the lines in row. By this setup, a gate oxide film is kept uniform in thickness, and a non-volatile semiconductor memory device of this constitution can be prevented from varying in electron injection characteristics.

10. 发明专利

JPH07169282A NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH07169282A
公开(公告)日：1995-07-04
申请号：JP31471293
申请日：1993-12-15
申请人： HITACHI LTD
发明人： TANAKA TOSHIHIRO , KATO MASATAKA , YOSHIDA KEIICHI , KUME HITOSHI , NAKAGOME YOSHINOBU , KIMURA KATSUTAKA
IPC分类号： G11C17/00 , G11C8/08 , G11C16/06 , G11C16/08 , G11C16/12
摘要： PURPOSE:To increase operational speed for rewriting action of a non-volatile semiconductor memory driven by single power supply voltage and to miniaturize the device by decreasing the number of transistors constituting a sub-word decoder circuit. CONSTITUTION:Sub-word decoder circuits WDi1-WDij drive word lines Wi1-Wij. A block selection address signals Bip and Bin generated from a first address signal group are made to be power supply voltage of an inverter circuit for controlling voltage of word line, and a gate selection address signal Gj generated from a second address signal group is connected to a gate input signal.

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