专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2581548B2 失效
公开(公告)号：JP2581548B2
公开(公告)日：1997-02-12
申请号：JP24225186
申请日：1986-10-13
申请人： HITACHI LTD
发明人： FUKAMI AKIRA , WATANABE TOKUO , PPONMA HIDEO , NAGANO TAKAHIRO , MONMA NAOHIRO , IKEDA TAKAHIDE , MISAWA YUTAKA
IPC分类号： H01L27/06 , H01L21/331 , H01L21/8249 , H01L29/72 , H01L29/73 , H01L29/732

2. 发明专利

JPH06120484A GATE TURN-OFF THYRISTOR 失效
公开(公告)号：JPH06120484A
公开(公告)日：1994-04-28
申请号：JP22967292
申请日：1992-08-28
申请人： HITACHI LTD
发明人： NAGANO TAKAHIRO
IPC分类号： H01L29/74 , H01L29/744
摘要： PURPOSE:To provide excellent turn-off performance which is not deteriorated from a prior art GTO without means for reducing a life time by forming an nE layer as a slender region, providing a pE layer directly under the slender region and providing an n type layer near the nE layer side from the pE layer on a periphery of the pE layer. CONSTITUTION:An nE layer 15 is formed of a plurality of slender regions 151, which are isolated from each other by a pE layer 14. A pE layer 12 is disposed adjacent to the other main surface 112, and so provided on a periphery of the region 151 that, when the regions 151 of the layer 15 are projected to the other main surface, a position crossed with one main surface 111 of a p-n junction between the region 151 and the layer 14 is superposed with the layer 12. An n type region 19 having the same conductivity type as that of an nE layer 13 and higher impurity concentration than that of the layer 13 is exposed on the surface 112. Thus, removal of stored carrier at the time of turning OFF is accelerated to realize a GTO having excellent turning-off performance.

3. 发明专利

JPH0626252B2 失效
公开(公告)号：JPH0626252B2
公开(公告)日：1994-04-06
申请号：JP27325285
申请日：1985-12-06
申请人： HITACHI LTD
发明人： KOBAYASHI YUTAKA , YAZAWA YOSHIAKI , FUKAMI AKIRA , NAGANO TAKAHIRO
IPC分类号： H01L29/78 , H01L27/12 , H01L29/786 , H01L29/784

4. 发明专利

JPH04362813A GATE CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, ITS MANUFACTURE, SEMICONDUCTOR STORAGE DEVICE AND MICROPROCESSOR 失效
公开(公告)号：JPH04362813A
公开(公告)日：1992-12-15
申请号：JP13880791
申请日：1991-06-11
申请人： HITACHI LTD
发明人： MINAMI MASATAKA , HIRAKI MITSURU , YANO KAZUO , WATANABE TOKUO , SEKI KOICHI , NAGANO TAKAHIRO
IPC分类号： G11C11/417 , H03K19/08
摘要： PURPOSE:To realize a gate circuit capable of operation even with a small MOSFET by supplying current respectively to the base of a PNP and an NPN transistor(TR) through the MOSFET till the output reaches a full amplitude and interrupting a path between the base and a power supply so as to discharge the charge stored in the base through a resistor. CONSTITUTION:When an input signal is set to a low level, a PMOS 104 is turned on and an NMOS 101 is turned off. When the output is set to a high level, a low level signal fed back by a CMOS inverter composed of a PMOS 107 and an NMOS 108 is inputted to the gate of a PMOS 103 and an NMOS 102 to turn on the PMOS 103 and to turn off the NMOS 102. Thus, the base of an NPN TR 106 and a power supply voltage terminal 3 are conductive, the TR 106 reaches the ON state offering a low impedance and the charge is strongly discharged to a capacitive load (not shown) from the output terminal 2. Moreover, a MOS 101 or 104 driving a bipolar TR 105 or 106, 107 applies a power supply voltage fully between the gate and the source.

5. 发明专利

JPH04349659A SEMICONDUCTOR INTEGRATED CIRUCIT DEVICE 失效
公开(公告)号：JPH04349659A
公开(公告)日：1992-12-04
申请号：JP12344991
申请日：1991-05-28
申请人： HITACHI LTD
发明人： MATSUZAKI NOZOMI , WATANABE TOKUO , MINAMI MASATAKA , SATO KAZUE , SHOJI KENICHI , NAGANO TAKAHIRO , MEGURO SATOSHI , YOSHIZUMI KEIICHI
IPC分类号： H01L27/06 , H01L21/331 , H01L21/8228 , H01L21/8249 , H01L27/082 , H01L29/41 , H01L29/73 , H01L29/732
摘要： PURPOSE:To obtain a C-BiCMOS semiconductor integrated circuit device in which logic gate circuits having fewer possible malfunctions are used, by providing, etc., a high-melting point metal lifting layer formed from the surface of at least one P-type well up to a high-density buried layer so as to surround each P-type well. CONSTITUTION:A semiconductor integrated circuit device of this invention is a kind of device which has BiCMOS construction and has CMOS transistors and bipolar transistors arranged mixed on the same substrate, and it has a plurality of P-type high-density buried layers 711 formed on a semiconductor substrate and a plurality of P-type wells 714 formed on each high-density buried layer 711. Besides, it has a high melting point metal lifting.layer 7725 formed from the surface of at least one P-type well 714 up to the high-density buried layer 711 so as to surround each P-type well 714, and a PNP transistor formed on the surface of the P-type well surrounded by the lifting layer 7725 so as to make the well 714 function as its collector.

6. 发明专利

JPH04123468A STATIC RAM TYPE INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04123468A
公开(公告)日：1992-04-23
申请号：JP24236690
申请日：1990-09-14
申请人： HITACHI LTD
发明人： HONMA HIDEO , SAWAHATA YASUO , MINAMI MASATAKA , WATANABE TOKUO , NAGANO TAKAHIRO
IPC分类号： H01L29/78 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To perform an SRAM cell type semiconductor integrated circuit device having a high speed, high integration, high reliability by providing a shielding electrode to separate between elements in an SRAM cell, and reducing in thickness an insulating film between electrodes of a part in which the electrode and a gate electrode are overlapped, under the gate electrode of a driver MOSFET as compared with that of a transfer MOSFET. CONSTITUTION:In an SRAM in which a cell is composed of at least four or more MOSFETs in a semiconductor substrate, a shielding electrode 4 is provided on a region for isolating between the MOSFETs, and an insulating film between the electrodes of the MOSFETs at a part in which the gate electrodes of the MOSFETs and the shielding electrode are overlapped, is reduced in thickness under the gate electrode of a driver MOSFET as compared with that of a transfer MOSFET. In an SRAM in which a CMOS memory cell is composed of at least six or more MOSFETs in a semiconductor substrate, a shielding electrode is provided on a region for isolating between the MOSFETs, the shielding electrode is formed of a p type polycrystalline silicon layer on a p-well region and an n type polycrystalline silicon layer on an n-well region. Further, in order to prevent the shielding electrode and the gate electrode from being short-circuited, at least upper and lower surfaces of the shielding electrode are covered with silicon nitride films.

7. 发明专利

JPH03114267A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH03114267A
公开(公告)日：1991-05-15
申请号：JP25047889
申请日：1989-09-28
申请人： HITACHI LTD
发明人： WATANABE TOKUO , SATO KAZUE , NAGANO TAKAHIRO
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/768 , H01L21/8238 , H01L23/52 , H01L23/522 , H01L27/092 , H01L29/43 , H01L29/78
摘要： PURPOSE:To connect diffused layers in mutually different conductivity type formed in a substrate in stable state by a method wherein a silicide layer connected to diffused layers is formed on the surface of openings formed in an insulating film and a polycrystalline silicon as well as on the surface of the polycrystalline silicon. CONSTITUTION:Openings in diameter of about 0.5mum are made in the upper parts of a P layer 30 and an N layer 20 out of a P polysilicon film 6 and then a gate film 5 beneath the said openings is etched away using fluoric acid water solution to form connecting holes 7. Next, the whole surface is coated with a tungsten silicide (WSi2) film 8 1000Angstrom thick by sputtering process. At this time, in the said connecting holes 7, the WSi2 film 8 is directly ohmic connected with the P layer 30 and the N layer 20. Finally, a connecting wiring 9b and gate electrodes 9a are completed by processing the P polysilicon layers 6 and the WSi2 film 8 in specified shape by dryetching process in high anisotropy using an etching gas mainly comprising carbon tetrachloride.

8. 发明专利

JPH0334468A INSULATED GATE TYPE FIELD-EFFECT SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0334468A
公开(公告)日：1991-02-14
申请号：JP16669989
申请日：1989-06-30
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： SHIODA MASASHI , NAGANO TAKAHIRO , OBAYASHI MASAYUKI
IPC分类号： H01L29/78
摘要： PURPOSE:To reduce the lowering of a breakdown strength between a source and a drain even when a threshold voltage is lowered, by a method wherein the position of a maximum impurity concentration is made deep inward from a surface and an impurity concentration of the surface is made lower than the maximum impurity concentration in the impurity concentration distribution of a channel region being opposite to a gate electrode with a gate insulation film formed therebetween. CONSTITUTION:With a gate electrode 9a and a resist film 3 used as a mask, impurity boron (B) ions of a reverse conductivity type to the one of an impurity in a drain region are implanted from the surface of an N-type Si layer 2a. Next, boron (B) is diffused down below the gate electrode 9a by thermomigration, so as to form a P-type channel region 6a. Herein, a region being opposite to the gate electrode, with a gate Si oxide film 8a formed therebetween, in the P-type channel region 6a is formed by transverse diffusion of the boron in a state just after the ion implantation, used as a source of diffusion. Therefore, the position of a maximum impurity concentration is deep inward from the surface of the P-type channel region 6a even in the region opposite to the gate electrode 9a with the gate Si oxide film 8a between, and an impurity concentration of the surface is lower than the maximum impurity concentration.

9. 发明专利

JPH02246264A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH02246264A
公开(公告)日：1990-10-02
申请号：JP6798589
申请日：1989-03-20
申请人： HITACHI LTD
发明人： MINAMI MASATAKA , SATO KAZUE , WATANABE TOKUO , YADORI SHOJI , NISHIDA TAKASHI , NAGANO TAKAHIRO
IPC分类号： H01L21/8249 , H01L27/06 , H01L27/11
摘要： PURPOSE:To make it possible to arrange MOS transistors in the close proximity and to improve the integration density of a device by forming the base electrode of a bipolar transistor in the same step at either of the step for foming P-type or N-type polycrystalline silicon layer. CONSTITUTION:The following steps are provided: the step for forming the gate electrode of one MOS transistor Q1 with a P-type polycrystalline silicon layer 9; the step for covering the side surface of the P-type polycrystalline silicon layer 8 with an insulating film 12; and the step for forming the gate electrode of another MOS transistor Q2 with an N-type polycrystalline silicon layer 10. A base electrode B of a bipolar transistor is formed in the same step as the step for forming either of the P-type polycrystalline silicon layer 9 or the N-type polycrystalline silicon layer. Thus, the high integration density of the device can be achieved without increasing the manufacturing steps.

10. 发明专利

JPH0286163A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0286163A
公开(公告)日：1990-03-27
申请号：JP23634988
申请日：1988-09-22
申请人： HITACHI LTD
发明人： OBAYASHI MASAYUKI , NAGANO TAKAHIRO
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/095
摘要： PURPOSE:To miniaturize a semiconductor element by constituting all of the junctions formed in regions in adjacency, among source regions and drain regions of FET's, by Schottky junctions. CONSTITUTION:In a P-type well region 2 and an N-type well region 3, electrodes 11-1, 11-3 composed of titanium nitride are formed by sputtering in a nitrogen atmosphere. The electrode 11-3 and the electrode 11-1 are connected with VDD and VSS, respectively. When an input is VSS level, an inversion layer is formed on the surface from the junction part with the electrode 11-3 to the junction part with the electrode 11-2; the potential barrier generated by a Schottky junction vanishes, and a P-channel MOSFET 51 turns ON. At this time, in an N-channel MOSFET 41, a bias voltage is not applied between a gate electrode 6-1 and the P-type well 2, so that a Schottky junction is formed as it is and the MOSFET 41 turns OFF. On the contrary, when the input shows VDD level, the inversion layer is formed on the surface of the P-type well 2, so that the output voltage attains Vss level.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式