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    • 8. 发明专利
    • CONTROL UNIT FOR WAITER
    • JPH04189269A
    • 1992-07-07
    • JP31392790
    • 1990-11-21
    • HITACHI LTD
    • SAKATA KAZUHIRONAKAZAWA SATOSHI
    • B66B1/14B66B1/46B66B3/00
    • PURPOSE:To allow a dumb waiter to be immediately operated on any floor by the operation of a specified person by removing a designation call button from an operation board on each floor, and moving it to a portable device having an infrared remote controller formed for exclusive use. CONSTITUTION:A designation call button constituting a call registering means in an operation board 26 on each floor is removed, the designation call button is provided in a portable device 45 having an infrared remote controller integrated thereto, and the infrared remote control signal of this portable device 45 is received by a receiver device 48 provided on the side of a hatch 42 for carrying in and out a load on each floor. Namely, as the operation is conducted by the remote controller 45 formed for exclusive use, only a person using the remote controller 45 can operate a dumb waiter, and the same effect as the operation by a key is obtained. Thus, as the operation can be conducted on any floor if the person has only the remote controller 45, there is no necessity for the person to go to a specified floor each time to conduct the key operation.
    • 9. 发明专利
    • RESET CIRCUIT FOR DIGITAL SYSTEM
    • JPH03256108A
    • 1991-11-14
    • JP5367290
    • 1990-03-07
    • HITACHI LTD
    • KASAI SHOJIHIROSE MASAYUKISAKATA KAZUHIROSUGIYAMA MASAO
    • G06F1/24
    • PURPOSE:To prevent the generation of runaway in a microprocessor or miswriting in a memory by connecting a voltage monitoring IC with a a low operation power supply voltage to the output of the other voltage monitoring IC so that these ICs are used for resetting the microprocessor and turning on/off a power supply for the memory. CONSTITUTION:The voltage monitoring IC 1 is connected to the output of the voltage monitoring IC 2 with the low operation power supply voltage, the node between both the ICs 1, 2 is connected to the reset terminal of the microprocessor 3, a reset line L6 inputted to the chip select (CS) terminals of respective memories 5, a decoding circuit 4 for decoding an address bus L9, and the output lines L8 of the circuit 4 are connected to the other CS terminals of respective memories 5, and the micropocessor 3 and the memories 5 are connected to a data bus L7. When the operation of the IC 1 exceeds the operable voltage point (a) of the processor at the rise of the power supply, a reset signal is outputted. The reset signal is outputted before the IC 2 arrives at the point (a). Thereby, an OR logic between the outputs of the ICs 1, 2 is outputted to the line L6. Since the IC 1 is reset before the operation of the microprocessor 3, the microprocessor 3 can be prevented from generating runaway.