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1. 发明专利

JPH06319263A INVERTER APPARATUS 失效
公开(公告)号：JPH06319263A
公开(公告)日：1994-11-15
申请号：JP21028191
申请日：1991-07-26
申请人： HITACHI LTD , HITACHI TECHNO ENG
发明人： MATSUI TAKAYUKI , HORIE SATORU , SAITO HIDEJI , TOYODA EIICHI , SAKATA KAZUHIRO , KAWAKAMI TETSUYA , ANDO TAKESHI , TSUBOI TAKASHI , NAKAMURA KIYOSHI , NAKADA KIYOSHI , TSUTSUI YOSHIO , TANAMACHI TOKUNOSUKE
IPC分类号： B60L9/16 , H02M7/48 , H02M7/497 , H02M7/515 , H02P27/06 , H02P27/08 , H02P7/63
摘要： PURPOSE:To prevent overcurrent and the stoppage of operation by generating a PWM signal with a DC power supply having a neutral point and providing a short-circuit detector and a switch for every unit inverter at the time of driving a multiple inverter having a plurality of unit inverters. CONSTITUTION:A voltage command arithmetic unit 4 generates three-phase AC voltage commands VU* to VW* from a DC power supply having a neutral point with a frequency command f1, and it is inputted to a PWM signal arithmetic unit 3. The arithmetic unit 3 generates a PWM signal to drive a multiple inverter 1 made up of a plurality of unit inverters. The multiple inverter 1 outputs a three-phase AC to rotate a motor 2. A filter circuit 5 detects a current or a voltage for every unit inverter of the multiple inverter 1 to output it to an absolute-value circuit 6. The absolute value sought in the circuit 6 is added 7 to a reference signal SC* to output a deviation to a decision device 8. The unit inverter in which the deviation is not less than a predetermined value is determined to be in the fault phase to fix an output at a zero by opening a path from a direct-current circuit. Thereby, the operation thereof is continued with the remaining sound phases.

2. 发明专利

JPH04334976A INVERTER AND DRIVE SYSTEM FOR AC MOTOR 失效
公开(公告)号：JPH04334976A
公开(公告)日：1992-11-24
申请号：JP10411491
申请日：1991-05-09
申请人： HITACHI LTD , HITACHI TECHNO ENG
发明人： MATSUI TAKAYUKI , HORIE SATORU , KAWAKAMI TETSUYA , SAITO HIDEJI , TOYODA EIICHI , SAKATA KAZUHIRO , TSUBOI TAKASHI , NAKAMURA KIYOSHI , NAKADA KIYOSHI , TSUTSUI YOSHIO , TANAMACHI TOKUNOSUKE
IPC分类号： B60L3/00 , B60L9/22 , H02H7/122 , H02M7/483 , H02M7/497 , H02P27/06
摘要： PURPOSE:To eliminate the overcurrent due to an erroneous firing and produce a low-harmonic a.c. output by providing a means for switching between two modes that have, respectively, two and three a.c. phase voltage levels. CONSTITUTION:A switch 8 judges the timing of switching between 3-level mode and 2-level mode in response to an inverter output command. After a judgment, the switch 8 supplies an output to a series multiple inverter 4, an indicator 4, and PWM signal processor 18. This completes an operation of switching. If an erroneous firing occurs, a current including a large d.c. component. flows, and the current is led to a neutral point in a d.c. circuit through a diode that connects the neutral point and a switching element. The overcurrent flows to the neutral point along the broken line shown. The magnitude of this d.c. current is limited by reactors 45 and 47. As a result, the overcurrent due to an erroneous firing is prevented, and it is thus possible to produce a low- harmonic a.c. output useful environment involving a lot of noise.

3. 发明专利

JPS62203566A CONTROLLER FOR PULSE-WIDTH MODULATION TYPE INVERTER 失效
公开(公告)号：JPS62203566A
公开(公告)日：1987-09-08
申请号：JP4182686
申请日：1986-02-28
申请人： HITACHI LTD , HITACHI TECHNO ENG
发明人： TERUNUMA MUTSUHIRO , KAWAKAMI TETSUYA , NAKAMURA KIYOSHI
IPC分类号： H02M7/48
摘要： PURPOSE:To prevent a current from varying and a torque from altering in a pulse-width modulation type inverter by providing a double buffer latch at the input side of a modulation percentage signal or an inverter frequency to simultaneously set the inverter frequency, a number-of-pulse signal and the modulation percentage signal. CONSTITUTION:The data bus 1a of a microcomputer 1 is connected in parallel with VC1 latch 2a and an FIV latch 3, and the output of the VC1 latch 2a is connected with a VC2 latch 2b to form a double buffer latch. When inputting a frequency latch pulse 3b, the latch 3 outputs an inverter frequency signal 4a and a number-of-pulse signal 4b. The signal 4b is converted by a D/F converter 5 to a frequency, a modulation wave data half period is divided by 3 by a sweep counter 6 together with the signal 4b to form clock signal for sweeping the addresses of ROMs 7a'7c. Data from the ROMs 7a-7c are supplied through comparators 8a-8c to a waveform combining PWM signal generator 10.

4. 发明专利

JPH01321864A CONTROLLER FOR PULSE WIDTH MODULATING SYSTEM INVERTER 失效
公开(公告)号：JPH01321864A
公开(公告)日：1989-12-27
申请号：JP15241888
申请日：1988-06-22
申请人： HITACHI LTD , HITACHI TECHNO ENG
发明人： TERUNUMA MUTSUHIRO , NAKAMURA KIYOSHI , TOYODA EIICHI , KAWAKAMI TETSUYA
IPC分类号： B60L9/18 , H02M7/48 , H02M7/515
摘要： PURPOSE:To prevent the deterioration of the withstand voltage of a switching element by providing all switching elements in one of upper or lower arm of a main circuit with ON signal prior to the gate start of an inverter upon starting the gate of the inverter. CONSTITUTION:A DC power, supplied from a trolley wire through a pantograph and a LC filter circuit, is converted into 3-phase AC power by a VVVF inverter device, consisting of a main circuit TM, a PWM signal control unit PC, a gate signal generating unit GG and the like, and is supplied to an induction motor M to run an electric car. The torque of the motor M is determined by a slip frequency Fs and, therefore, an inverter frequency is obtained by a motor current control unit CC and the like and pulse width modulation is effected through the PWM signal control unit PC. In this case, the GTOs of all phases, existing in one of a main circuit arm, are provided with ON signals simultaneously and, thereafter, the gates are started. According to this method, the deterioration of the withstand voltage of switching elements may be prevented upon the arc-extinguishing of said GTOs.

5. 发明专利

JPS62110404A CONTROLLER FOR INDUCTION MOTOR DRIVEN ELECTRIC ROLLING STOCK 失效
公开(公告)号：JPS62110404A
公开(公告)日：1987-05-21
申请号：JP24887485
申请日：1985-11-08
申请人： HITACHI LTD , HITACHI TECHNO ENG
发明人： KAWAKAMI TETSUYA , NAKAMURA KIYOSHI , TOYODA EIICHI
IPC分类号： B60L9/18
摘要： PURPOSE:To obtain a brake with a superb adhesive performance by providing a means to normalize the output of speed detective means for each induction motor in accordance with the difference of each wheel diameter. CONSTITUTION:A normalized arthmetic logic unit 7 measures the deviation on the basis of a certain shaft when all the shafts are rotating without idling or sliding as in coasting. The reciprocal of this deviation is stored in factor memories 81-84. In the subsequent power running or regeneration, with the memorized value as the corrective factor the speed detection values fr1-fr4 are obtained which are normalized by multiplying the output fr01-fr04 of a speed detector 31-34. From among the normalized speed detection values fr1-fr4, the minimum value in power running and the maximum value in braking are selected to introduced a rotor frequency fr, to or from which a slip frequency fs set out by a slip frequency setting adjuster 6 is added or subtracted to let it an inverter frequency fINV.

6. 发明专利

JP2004080994A Power conversion apparatus of electric vehicle 有权
公开(公告)号：JP2004080994A
公开(公告)日：2004-03-11
申请号：JP2003322577
申请日：2003-09-16
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKADA KIYOSHI , TANAMACHI TOKUNOSUKE , NAKAMURA KIYOSHI , TERUNUMA MUTSUHIRO , SUZUKI MASAHITO , TSUTSUI YOSHIO , TOYODA EIICHI
IPC分类号： B60L9/18 , H02M7/48 , H02M7/497 , H02P27/06 , H02P27/08 , H02P7/63
摘要： PROBLEM TO BE SOLVED: To prevent a sound of discontinuity, by making output voltage of a three-level inverter controllable from zero to maximum, to realize generation control of a three-level pulse continuously further smoothly performing output voltage of the inverter.
SOLUTION: The power conversion apparatus of the electric vehicle, comprising a power converter converting DC voltage into AC phase voltage having a three-level potential which is positive/negative intermediate voltage and a control device acceleration/ deceleration controlling an AC electric motor connected to an output side of this converter, is constituted by providing a first pulse width modulation control region, alternately outputting a positive/negative voltage pulse through the intermediate voltage over the half period total region of a fundamental wave of output voltage of the converter, in a low-speed region in acceleration/deceleration control and a second pulse width modulation control region, having a first period continuously outputting a plurality of voltage pulses of the same polarity in the half period of the output voltage fundamental wave of the converter, and a second period alternately outputting the positive/negative voltage pulse through the intermediate voltage before/after this first period in a high speed region in the acceleration/deceleration control.
COPYRIGHT: (C)2004,JPO

7. 发明专利

JPH10323055A POWER CONVERTER 失效
公开(公告)号：JPH10323055A
公开(公告)日：1998-12-04
申请号：JP11815798
申请日：1998-04-28
申请人： HITACHI LTD
发明人： NAKADA KIYOSHI , TANAMACHI TOKUNOSUKE , NAKAMURA KIYOSHI , TERUNUMA MUTSUHIRO , SUZUKI MASAHITO , TSUTSUI YOSHIO , TOYODA EIICHI
IPC分类号： B60L9/18 , H02M7/48 , H02M7/483 , H02P27/08 , H02P7/63
摘要： PROBLEM TO BE SOLVED: To attain continuous and smooth control of an inverter output voltage, by computing the rising and falling and the timing of the rising and falling of pulses for the positive-side and negative-side switching elements of a power converter interchangeably. SOLUTION: A multiple pulse generating means 1 outputs a dipolar modulated waveform, or unipolar modulated waveform, or overmodulated waveform according to output voltage related information and shift control information. A one- pulse generating means 2 outputs (one pulse mode) a one-pulse waveform according to the output voltage related information. A shift controlling means 3 shifts each PWM mode continuously. Gate signals to be the outputs of the shift controlling means 3 are given to the switching elements in each-phase (U-phase, V- phase, W-phase) switching unit 7a, 7b, 7c through gate amplifiers, and on-off control is performed. Consequently, it becomes possible to adjust the output voltage of the inverter from zero to a maximum voltage continuously and smoothly.

8. 发明专利

JPH09219974A POWER CONVERTER 失效
公开(公告)号：JPH09219974A
公开(公告)日：1997-08-19
申请号：JP6770997
申请日：1997-03-21
申请人： HITACHI LTD
发明人： NAKADA KIYOSHI , NAKAMURA KIYOSHI , TANAMACHI TOKUNOSUKE , TSUTSUI YOSHIO , TERUNUMA MUTSUHIRO
IPC分类号： H02M7/483 , H02M7/5387 , H02M7/48
摘要： PROBLEM TO BE SOLVED: To decrease the higher-harmonic-wave current flowing from the side of an AC voltage to an AC power supply by connecting the series connecting points of voltage divider capacitors in respective phases and the dividing points of corresponding switching arms in respective phases, and connecting the series connecting points of the voltage divider capacitors in respective phases. SOLUTION: Voltage divider capacitors 3a-3c are independently provided for every phase. The voltage divider capacitors 3a-3c in respective phases are arranged in the vicinities of switching arms 2a-2c in individual phases, respectively. Intermediate potential points Oca-Occ, which are the series connecting points of the voltage divider capacitors in respective phases, and the connecting points of auxiliary rectifying elements D5a, D6a-D5c and D6c, that is to say, the dividing points of the switching arms 2a-2c in respective phases, are connected. In this way, the intermediate potential points Oca-Occ of the voltage divider capacitors 3a-3c in respective phases are connected between the respective phases. Thus, the higher-harmonic-wave current flowing from the side of the AC voltage to the AC power supply can be decreased.

9. 发明专利

JPH09191660A POWER CONVERTER 失效
公开(公告)号：JPH09191660A
公开(公告)日：1997-07-22
申请号：JP29996
申请日：1996-01-05
申请人： HITACHI LTD
发明人： NAKADA KIYOSHI , SAITO HIDEJI , NAKAMURA KIYOSHI
IPC分类号： H01L25/07 , H01L25/18 , H02M1/00 , H02M1/06 , H02M7/48
摘要： PROBLEM TO BE SOLVED: To provide a power converter capable of suppressing the wiring length of a main circuit and that of a snubber circuit to the minimum, and capable of having small-sized simple mounting structure. SOLUTION: A module type power semiconductor devices 1A, 1B incorporating self-arc-extinguishing semiconductor devices and snubber capacitors have the collector terminals C and the emitter terminals E1 of the self-arc- extinguishing semiconductor devices, and the anode terminals A and the cathode terminals K of the snubber diodes provided independently respectively, and they are arranged in such a way that the collector terminals C and the emitter terminals E1 may be on both sides of the anode terminals A and the cathode terminals K of the snubber diodes. As the result of this, it becomes possible to cause the module type power semiconductor devices 1A, 1B to have the same terminal arrangement, and besides to linearize and simplify wiring by a positive electrode P side wiring member 4, a negative electrode N side wiring member 5, and a wiring member 6 for AC output, and to simplify the connection with a snubber capacitor module 2 also.

10. 发明专利

JPH0775345A POWER CONVERTER DEVICE 失效
公开(公告)号：JPH0775345A
公开(公告)日：1995-03-17
申请号：JP21718593
申请日：1993-09-01
申请人： HITACHI LTD
发明人： NAKADA KIYOSHI , TERUNUMA MUTSUHIRO , TANAMACHI TOKUNOSUKE , NAKAMURA KIYOSHI
IPC分类号： B60L9/22 , H02M7/48 , H02M7/483 , H02M7/497 , H02M7/515 , H02M7/5387
摘要： PURPOSE:To make a capacitor voltage uniform by regulating a zero voltage period on the basis of the polarity of the output current of a power converter device and a differential voltage of capacitors connected in series. CONSTITUTION:A pulse width modulating means 1 outputs output timings (OT) Tup, Tun, Tvp, Tvn, Twp and Twn of the phases. A differential voltage detecting means 3 determines a differential voltage DELTAVc of divided capacitor voltages Vcp and Vcn by a subtracter 30, detects then a low frequency component DELTAVc by a low-pass filter 31 and generates a basic correction width DELTAT by a gain regulator 32. Polarity detecting means 41 to 43 detect the polarities of motor currents iu, iv and iw. They output +1 when the polarities are positive, and output -1 when they are negative. Compensation widths (PD) DELTATu to DELTATw of pulse timings of the phases are determined by multiplying the outputs of the polarity detecting means 41 to 43 by the basic correction width DELTAT. A pulse timing corrector 40 executes OT correction on the basis of PD DELTATu to DELTATw and OT Tup to Twp and information on an operation mode and outputs the result to a pulse output means 2.

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