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1. 发明专利

JPS634498A MEMORY DEVICE 失效
公开(公告)号：JPS634498A
公开(公告)日：1988-01-09
申请号：JP14697786
申请日：1986-06-25
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KEIDA HARUO , KIMURA SADAO
IPC分类号： G11C17/00 , G11C16/02
摘要： PURPOSE:To back up required data by writing the required data in other memory block to make its memory block usable when the number of times of rewrite/erasure in and from one unit memory block reaches a prescribed number of times. CONSTITUTION:A microcomputer unit MCU, at each operating cycle, discriminates whether the operation is write operation in unit memory blocks MB1-MBi. When it is discriminated to be write operation, the microcomputer unit MCU reads count data from a prescribed counter register CR first and discriminates whether or not the count data reaches a preset value. When it is discriminated that the data reaches the prescribed value, the microcomputer unit MCU reads all data stored in the memory block MB1 sequentially. Then the read data is stored sequentially in the next memory block MB2 to execute the backup of the required data.

2. 发明专利

JPH047646A DATA PROCESSOR 失效
公开(公告)号：JPH047646A
公开(公告)日：1992-01-13
申请号：JP10756890
申请日：1990-04-25
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , HITACHI MICRO SOFTWARE SYST
发明人： KIMURA SADAO , TANAKA TOSHIKAZU , SHIMADA YUJI
IPC分类号： G06F11/22 , G06F13/00
摘要： PURPOSE:To dispense with an externally attached error generating device, and simultaneously, to facilitate the software debug of an error processing program by providing a built-in error generating state forming means. CONSTITUTION:An SCSI (small computer system interface) 40 includes an SCSI controller 2 and a CPU (central processing unit) 3, and the SCSI controller 2 includes an interface unit 6, the error generating state forming means 7, and a NOR gate 28. Then, the error generating state forming means 7 is provided with a function to form forcedly the generating state of an error, for instance, a parity error. Thus, the error generating device need not be outside arranged, and simultaneously, the software debug at the time of the occurrence of the error can be facilitated.

3. 发明专利

JPH03156642A BRANCH ADDRESS CONTROLLER 失效
公开(公告)号：JPH03156642A
公开(公告)日：1991-07-04
申请号：JP29507289
申请日：1989-11-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KIMURA SADAO , TANAKA TOSHIKAZU , KUMASAKA KUMIKO
IPC分类号： G06F9/48 , G06F9/46
摘要： PURPOSE:To perform a software branching process at a high speed by selecting the head address of the corresponding unit software out of a holding means in accordance with the combination of plural types of conditional information and independently of a processor and then selecting the head address of the transfer destination unit software. CONSTITUTION:The head addresses are individually held by the address registers AR1 - AR6, and a decoder 7 decodes plural types of conditional information, i.e., the signals, the inverse of I/O, the inverse of C/D and the inverse of MSG for transfer of the information transfer phase. Then the corresponding head address information are read out of the registers AR1 - AR6 with a produced selection signal. These read address information are held by a head address register AR7. Thus, a CPU 2 decides successively the signals, the inverse of I/O, the inverse of C/D and the inverse of MSG in transfer to another phase. Thus no decision is required for the transfer destination phase, and the software can be quickly branched based on the contents held by the register AR7.

4. 发明专利

JPS6329847A DATA PROCESSOR 失效
公开(公告)号：JPS6329847A
公开(公告)日：1988-02-08
申请号：JP17167686
申请日：1986-07-23
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： TSUKAMOTO TAKU , KIMURA SADAO
IPC分类号： G06F9/46 , G06F9/48
摘要： PURPOSE:To attain rapid switching of a general register bank by forming a bank identification area storing bank identification data for specifying plural general register banks which can be switched and used in a program counter. CONSTITUTION:The bank identification (ID) area Ebr storing the bank ID data for selecting a prescribed register bank out of the register banks RB1-RB8 is formed in the program counter PC and the bank ID data are included in vectors stored in the program counter PC. Since the register bank an be switched only through vectoring of the program counter PC, a memory cycle is required only at the time of receding the program counter PC, the number of processing steps can be reduced and the switching of the register bank can be rapidly executed. Consequently, multi-task processing based upon interruption can be rapidly attained.

5. 发明专利

JPS6381569A DESIGN SYSTEM FOR MICROCOMPUTER 失效
公开(公告)号：JPS6381569A
公开(公告)日：1988-04-12
申请号：JP22601086
申请日：1986-09-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KITA YUTAKA , KIMURA SADAO , KEIDA HARUO , KIHARA TOSHIMASA
IPC分类号： G06F17/50
摘要： PURPOSE:To develop a microcomputer conforming to the requirements of user in a short period by forming a microprocessor section, a peripheral circuit and a memory circuit as modules having nearly the same lateral width and connecting the modules by a bus. CONSTITUTION:Plural types different in storage capacity are prepared for memory modules such as a mask ROM module, an EPROM module, an EEPROM module and a RAM module. Then the layout of each element and wiring is designed so that the lateral width of each module expanded into the circuit pattern is nearly constant. Then the wiring is applied so that input/output terminals of each circuit, that is, the entrance/exit of the signal are arranged on one side of each module at an equal interval or with regularity. Then the arrangement of the modules selected by the user is decided. In this case, the length of the wiring (bus) connecting the modules is designed as short as possible. Thus, the user can develop a microcomputer conforming to its requirements in a short period.

6. 发明专利

JPS634716A COUNTER CIRCUIT 失效
公开(公告)号：JPS634716A
公开(公告)日：1988-01-09
申请号：JP14695586
申请日：1986-06-25
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： CHIBA KATSUICHIRO , KIMURA SADAO , KEIDA HARUO
IPC分类号： H03K21/40 , H03K21/00 , H03K23/54
摘要： PURPOSE:To improve the testing efficiency of carry by providing a carry forcing circuit supplying a carry signal forcibly to a required flip-flop circuit except the first stage circuit in response to the of the test mode. CONSTITUTION:The carry forcing circuit Fenfo is placed to carry signal lines S1, S2 between binary counters CUNT7, CUNT8 in order to connect/disconnect the carry signal lines S1, S2 on the way at the high and low-order electrically and N-channel transfer MOSFETs Qf1, Qf2 are interposed. A test signal phitest is fed to gates of the transfer MOSFETs Qf1, Qf2. With the test signal phitest at a low level, it instructs the test mode. Thus, in instructing the test mode, the carry signal liens S1, S2 are separated into the low-order bytes and the high-order btes from the midpoint electrically. Thus, a ripple counter circuit counts the low-order and the high-order bytes in parallel.

7. 发明专利

JPH0492254A HARD DISK MEMORY DEVICE 失效
公开(公告)号：JPH0492254A
公开(公告)日：1992-03-25
申请号：JP20976490
申请日：1990-08-08
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TANAKA TOSHIKAZU , KIMURA SADAO
IPC分类号： G11B19/20 , G11B19/00
摘要： PURPOSE:To reduce power consumption by performing the rotary driving of a storage medium when no access is performed at speed slower than that when making access. CONSTITUTION:When the occurrence of an access request is detected by an access state detecting part 24 in a state where a motor 13 is idle-rotated at slow speed, a speed setting part 25 switches the control speed of the motor 13 to accessible constant high speed replying to above detection. Thereby, when the rotating speed of the motor 13 is increased to constant access speed, access for the read/write of storage information on the storage medium 1 is performed by the operations of a head driving control part 22 and a read/write circuit 23, etc. When the above access is completed, it is detected by the access state detecting part 24, and the speed control part 25 returns the control speed of the motor 13 to the above idle speed replying to the detection.

8. 发明专利

JPH06231278A MICROPROCESSOR 失效
公开(公告)号：JPH06231278A
公开(公告)日：1994-08-19
申请号：JP1324193
申请日：1993-01-29
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： OKI SATOMI , IDO SHINICHI , KIMURA SADAO , YAJIMA TOSHIYA
IPC分类号： G06F15/78
摘要： PURPOSE:To provide the microprocessor capable of the effective processing without deteriorating the high-speed performance of the microprocessor even when it comes to make an access to slow-access memories and peripheral devices. CONSTITUTION:The microprocessor which inputs and outputs data with the outside, memory connected to the outside, and an address latch circuit are provided. A data load instruction 9 of the microprocessor is divided into an address output instruction which simply outputs an address to an address bus and a simple load instruction which simply loads data from the data bus. Similarly, a data store instruction 10 is divided into an address output instruction and a simple store instruction. After the address is outputted, the data input/ output is requested to the memory. When the memory prepares for the input/ output of data, it executes other instructions, then the data exchange is executed with the memory.

9. 发明专利

JPH05298237A 失效
公开(公告)号：JPH05298237A
公开(公告)日：1993-11-12
申请号：JP9929492
申请日：1992-04-20
申请人： HITACHI LTD , HITACHI MICOM SYST KK , HITACHI MICRO SOFTWARE SYST
发明人： KIMURA SADAO , AKIMOTO OSAMU , YAMAZAKI YUKIE , SHIMADA YUJI , HOCCHI YASUO
IPC分类号： G06F13/24 , G06F13/36
摘要： PURPOSE:To simplify an external access to a controller without keeping an access requester CPU in an idle state for a long period of time by canceling the access limitation in accordance with the processing state of an LSi and informing the CPU of the cancel of the access limitation by means of a trap interruption request. CONSTITUTION:When a CPU 1 has an access request to an SCSi controller 3, a flag register 62 is set. Meanwhile, a decoder 61 decides the propriety of the access. Then the register 62 is reset when the decoder 61 decides an access enable state to cancel the access inhibition and at the same time this cancel is informed by a trap interruption request INT. The CPU 1 knows the cancel of the access inhibition to the controller 3 with the request INT. Then, the CPU 1 can have an access to the automatic processing function of the controller 3 by means an access given to an I/F register 4.

10. 发明专利

JPH04199320A DISK DRIVE CONTROL SYSTEM 失效
公开(公告)号：JPH04199320A
公开(公告)日：1992-07-20
申请号：JP33275290
申请日：1990-11-29
申请人： HITACHI LTD , HITACHI MICRO SOFTWARE SYST , HITACHI MICRO SYSTEM KK
发明人： YAMAZAKI YUKIE , SHIMADA YUJI , IZEKI TOSHIYUKI , HOCCHI YASUO , KIMURA SADAO , AKIMOTO OSAMU
IPC分类号： G06F3/06
摘要： PURPOSE:To shorten the average execution time of a command observed from a host side by parallelly executing data transfer between the host and buffer memory and data transfer between a disk drive device and the buffer memory to execute plural commands. CONSTITUTION:During executing the data transfer between a host 18 and a buffer memory 15 to execute one command, the data transfer between a disk drive device 13 and a buffer memory 15 for the other command execution or the seek processing of the disk drive device 13 are executed. In short, the restric tion for the combination of plural commands in a command queue is eliminated, and the data transfer between the host 18 and the buffer memory 15 and the data transfer between the disk drive device 13 and the buffer memory 15 are parallelly executed for executing plural commands. Thus, the average execution time of the command observed from the host 18 side can be shortened.

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