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1. 发明专利

JPH0443418A DATA PROCESSOR 失效
公开(公告)号：JPH0443418A
公开(公告)日：1992-02-13
申请号：JP15114490
申请日：1990-06-08
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： IMAI KOJU , TSUKAMOTO TAKU
IPC分类号： G11C11/401 , G06F1/24 , G11C11/406
摘要： PURPOSE:To shorten a development period and to reduce cost by providing a register composed of a flip flop where an initial state which is set by means of a reset signal can be altered by a control signal. CONSTITUTION:The control registers CTR is composed by using a flip flop whose set state and reset state can be switched by the control signal, and the control register CTR is initialized to the different initial state by the reset signal (r) in accordance with the state of a prescribed external terminal RES. In a microcomputer incorporated in a refresh controller, for example, the control register CTR is initialized in such a way that the refresh controller executes a conventional function at a regular operation mode, and the refresh controller is prevented from functioning in a test mode. Thus, the microcomputer incorporating the refresh controller and a microcomputer which does not incorporate it and which has the same architecture can be evaluated by using the same test pattern, and cost can be reduced.

2. 发明专利

JPH0476646A MICROPROCESSOR 失效
公开(公告)号：JPH0476646A
公开(公告)日：1992-03-11
申请号：JP18397790
申请日：1990-07-13
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： IMAI KOJU , TSUKAMOTO TAKU
IPC分类号： G06F12/04 , G06F12/00
摘要： PURPOSE:To obtain a microprocessor which is widely applied like an 8-bit and a 16-bit system by switching the increment number of refreshment addresses corresponding to the width of a data bus. CONSTITUTION:When a control signal (a) is logic '1', a counter output signal C0 is sent from an address terminal A0. The counter output C1 of a 2nd bit is sent from an address terminal A1. Counter outputs from C2 to CN are outputted from address terminals A2 - AN. Thus, the refreshing addresses corresponding to the 8-bit data bus width can be sent out. When the signal (a) is logic '0', the signal C0 is outputted from the terminal A0 irrelevantly to the signal C0. At this time, the output C0 is sent from the address terminal A1. The output C1 of a next bit is sent from the terminal A2. Similarly, the counter outputs from C2 to Cn are outputted from the terminals A3 - AN+1. Thus, the refreshing addresses can be sent out corresponding to the 16-bit data bus width.

3. 发明专利

JPH1185723A MICROCOMPUTER AND MOVING BODY COMMUNICATION EQUIPMENT 失效
公开(公告)号：JPH1185723A
公开(公告)日：1999-03-30
申请号：JP24843797
申请日：1997-09-12
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： IMAI TOMIO , IMAI KOJU , AMADA MASAKI
IPC分类号： G06F15/78 , G06F1/04 , G06F9/30
摘要： PROBLEM TO BE SOLVED: To provide technology for reducing power consumption while the whole performance of a microcomputer application equipment is kept as it is. SOLUTION: A table memory 19 where information for identifying instructions to which a high speed processing is requested and a high speed processing is not requested, and which are executed in CPU 10, are made into a table is provided. Whenever the instruction is fetched by CUP 10, the frequency of a clock signal is controlled based on information of the table memory 19. Thus, the frequency of the clock signal can be reduced in accordance with the instruction. Power consumption can be reduced while the whole performance of the microcomputer application equipment is kept as it is.

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