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1. 发明专利

JPH0388450A COMMUNICATION EQUIPMENT 失效
公开(公告)号：JPH0388450A
公开(公告)日：1991-04-12
申请号：JP15523190
申请日：1990-06-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKIYASU YOSHIHIRO , AMADA EIICHI , NAKAMURA KAZUNORI , TAKADA OSAMU , YAMAGA MITSUHIRO , SHIGESA HIDEHIKO , KOBAYASHI NAOYA , HIRAYAMA SATORU , IIYAMA TATSUTOU
IPC分类号： H04L13/08 , H04L12/813 , H04L12/815 , H04L12/863 , H04L12/951
摘要： PURPOSE:To attain reassembling of a message without causing abort of a reception cell due to a deficient memory area by utilizing the end of a data readout for a succeeding write cycle every time the data readout of one memory block is finished. CONSTITUTION:A main trunk LAN is constituted by a transmission line 100 and plural nodes (communication equipments) 200A-200F connecting in a ring with the transmission line 100. In the readout of a cell data as to one message, a cell data is read out based on an address read from a readout address queue in the first cycle and a cell data is read based on a succeeding address pointer read in the preceding cycle from a buffer memory for succeeding cycles, and an address representing a memory block from which the cell data is read is released for write operation of the cell data received succeedingly as an idle address. Thus, the message is reassembled without causing abort of the reception cell.

2. 发明专利

JPS6276840A NODE EQUIPMENT 失效
公开(公告)号：JPS6276840A
公开(公告)日：1987-04-08
申请号：JP21471985
申请日：1985-09-30
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAI ATSUSHI , NAKAMURA KAZUNORI , TAKIYASU YOSHIHIRO , USAMI NAGATOSHI , YAMAGA MITSUHIRO
IPC分类号： H04L12/18 , H04L12/433
摘要： PURPOSE:To attain the confirmation of transmission of multiple address information simply and effectively by providing a means erasing reply and transmitting the reply of reception failure when the reception of multiple address information is failed and the reply of the multiple address information comes from an upperstream and a means sending the reception fault obtained through the operation of reply specific bit. CONSTITUTION:Whether or not the information during reception is the multiple address information to be received by its own node is discriminated by a control section 5 and when it is discriminated to be the multiple address information to be received, the control section 5 uses a signal line 130 to instruct the selection of the data line 10 to a selection circuit section 3 and inputs the state of a buffer section 6 through a signal line 120. If the buffer section 6 is idle, a data is sent to the buffer section 6 through a data line 14. If the buffer section 6 is busy, the end of the multiple address information is detected and then the selection of the data line 11 is instructed through a signal line 130 to the selection circuit section 3 to erase the reply succeeding to the frame, and the reply of the reception failure is sent to the transmission line through the data line 11. Thus, sure multiple address communication is attained.

3. 发明专利

JPS6294037A TOKEN RING COMMUNICATION SYSTEM 失效
公开(公告)号：JPS6294037A
公开(公告)日：1987-04-30
申请号：JP23330085
申请日：1985-10-21
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAI ATSUSHI , NAKAMURA KAZUNORI , TAKIYASU YOSHIHIRO , USAMI NAGATOSHI
摘要： PURPOSE:To detect the presence of a node not fetching a frame by setting logical '1' to a node not fetching a busy bit sent in logical '0' into its frame and making the node fetching the frame normally unchanged. CONSTITUTION:A node 100 in a ring transmission line sends a reception frame to a data control circuit 3 via a reception section 2 from an input line 10 and when the own node is an address object of the frame, data are sent to a host computer via a buffer 4 and an interface circuit 6. A frame status is provided with a busy bit in addition to an address identification bit and a frame reception bit and when the frame is received normally, the busy bit is sent from the transmission section 1 as it is. When the buffer 4 is not idle and no data is received, the level of the busy bit is set to logical '1' and the data is sent from the transmission section 1.

4. 发明专利

JPS6248833A TOKEN SYSTEM 失效
公开(公告)号：JPS6248833A
公开(公告)日：1987-03-03
申请号：JP18727885
申请日：1985-08-28
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKIYASU YOSHIHIRO , TAKAI ATSUSHI , WADA KENICHI , USAMI NAGATOSHI , NAKAMURA KAZUNORI
摘要： PURPOSE:To attain less hardware and to obtain a token detecting a fault quickly by adopting a pattern system token in the communication controller of a network using token passing to an access system. CONSTITUTION:A pattern 1 specific to token is selected sequentially by a pattern selection section 2 in a token transmission section. An FCS logic arithmetic section 3 and an FCS code register 4 generate an FCS code from a pattern string and a selection signal from a pattern selection signal generating section 7 is used to send selectively the pattern of B-F 40-bit from an FCS selection section 6. A reception data Va subjected to serial/parallel conversion is compared sequentially by the comparison section 13 with B, C, D of the set token pattern 1 in the token reception section. When a timing generation section 14 receives the coincidence detection signal of the pattern B, the pattern C is selected and a pattern selection section 17 is controlled to select the pattern D by using the coincidence signal of the pattern C. The token reception is decided by using the result of comparison Vc, result Vd of FCS code check and FCS code reception timing signal Ve.

5. 发明专利

JPS6235733A COMMUNICATION CONTROLLER 失效
公开(公告)号：JPS6235733A
公开(公告)日：1987-02-16
申请号：JP17415385
申请日：1985-08-09
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAI ATSUSHI , NAKAMURA KAZUNORI , YAMAGA MITSUHIRO , TAKIYASU YOSHIHIRO
IPC分类号： H04L29/08 , H04L13/00 , H04L29/00
摘要： PURPOSE:To reset a deadlock by transferring a means which recognizes a demanding origin from received demand information and received demand information to a communication system controller to transmit received demand information to a receivable answer transmitting origin which already received it. CONSTITUTION:A network is constituted by plural nodes 7 which have interfaces 6 for a terminal 8 and a computer 9 and are connected by a transmission line 5 in a loop shape. Consequently, if for example, C knows that RR from B is caused by a deadlock, the B which transmits data to the C transmits the data to A after data reception processing and the A transmits data to C after data reception processing to finish data transfer. For the purpose of knowing the deadlock, demand information is transmitted to the RR transmitting origin unless data is received even a certain time after RR transmission and nodes which transmit the RR transmit the information one after another, so that the deadlock is decided when the information returns to the transmitting origin of the demand information.

6. 发明专利

JPH10145742A VIDEO INPUT AND OUTPUT DEVICE FOR VIDEO SERVER 失效
公开(公告)号：JPH10145742A
公开(公告)日：1998-05-29
申请号：JP29842596
申请日：1996-11-11
申请人： HITACHI LTD
发明人： ASAI MITSUO , ONODERA TAKESHI , MORITA KOICHI , YAMASHITA YOJI , INOMATA HIROFUMI , TAKIYASU YOSHIHIRO
IPC分类号： G06F13/00 , H04N5/765 , H04N5/93 , H04N7/16 , H04N7/173 , H04N21/226
摘要： PROBLEM TO BE SOLVED: To attain in real time the reproduction control of contents of a video server by inputting the control instructions which are issued to a VTR from a linear editing machine, a nonlinear editing machine and a transmission controller and then operating a video input/output device in response to those input instructions. SOLUTION: The VTR emulation software performs the input/output management of the serial port hardware 122 and also the inter-hardware transfer of data and its control. The codec hardware 121 digitizes or digitally compresses the input video and audio signals and produces the video data to temporarily store them in a buffer 211. A VTR emulator transfers the video data to a buffer 210 of a memory 20 from the buffer 211. At the same time, the video data of the buffer 210 which are transferred from the buffer 211 are transferred to a buffer 213 of the network hardware 123 via an I/O bus 206 in parallel to the transfer of video data performed between both buffers 211 and 210 or in time division.

7. 发明专利

JPH08331539A VIDEO TRANSMISSION/RECEPTION SYSTEM AND DEVICE USED FOR IT 失效
公开(公告)号：JPH08331539A
公开(公告)日：1996-12-13
申请号：JP13898595
申请日：1995-06-06
申请人： HITACHI LTD
发明人： IGAWA MASARU , ASAI MITSUO , SHIBATA KOICHI , TAKIYASU YOSHIHIRO , YAMADA YOSHIHIRO , ODA TOSHIYUKI , IKUSHIMA MAKOTO
IPC分类号： H04L12/54 , H04L12/58 , H04N1/42 , H04N7/16 , H04N7/173 , H04N21/238 , H04N21/239 , H04N21/442
摘要： PURPOSE: To reduce a frequency of use of a control signal for video data request from a reception terminal equipment in the video transmission/reception system and to eliminate fluctuation between a server and the reception terminal equipment. CONSTITUTION: The reception terminal equipment is provided with an FIFO memory 202, a decoder 203 reads video data from the memory 202 intermittently and sequentially to decode and reproduce the data. A data management equipment 204 checks a storage data amount of the FIFO memory 202 and sends a control signal of temporary stop request to the server when the data amount is a 1st reference level or over and sends a temporary stop release request to the server vie a communication equipment 201 when the amount is a 2nd reference level or below. Thus, the amount of the control signal from the reception terminal equipment to the server is reduced. An existing video CD reproducing device is used for a decoder 203 and a display device 207 of the reception terminal equipment.

8. 发明专利

JPH08280002A IMAGE INFORMATION COMMUNICATION SYSTEM 失效
公开(公告)号：JPH08280002A
公开(公告)日：1996-10-22
申请号：JP8226895
申请日：1995-04-07
申请人： HITACHI LTD
发明人： SAITO ATSUSHI , ASAI MITSUO , ONODERA TAKESHI , TAKIYASU YOSHIHIRO , IMAI YASUHIRO
IPC分类号： H04N5/765 , H04L12/28 , H04L12/70 , H04M11/08 , H04N7/173 , H04N21/436 , H04N21/643 , H04Q3/00
摘要： PURPOSE: To provide the image information communication system for VOD with which an image file away from a terminal can be accessed. CONSTITUTION: Filing devices 200-202 for storing image information and a server 1 are connected by a SCSI interface, and the server 1 is connected through converters 400-403 having ATM converting functions to communication lines. Besides, terminals 500-503 having SCSI interfaces are connected through similar converters 430-433 to the communication lines. Commands and data to be handled at the terminals depend on format based on the SCSI. Since video editing/sending is enabled under the environment that existent control softwares and applications can be applied, cost can be reduced. Further, since delivery interruption can be avoided in the case of video sending, reliability can be improved.

9. 发明专利

JPH0832598A STORAGE AND TRANSMISSION SYSTEM FOR CONTINUOUS MEDIA 失效
公开(公告)号：JPH0832598A
公开(公告)日：1996-02-02
申请号：JP16767194
申请日：1994-07-20
申请人： HITACHI LTD
发明人： KIN INKI , TAKIYASU YOSHIHIRO , ASAI MITSUO , SHIBATA KOICHI , SATOU MIKIKO , IGAWA MASARU
IPC分类号： H04Q3/00 , H04L12/28 , H04L12/70 , H04L12/951 , H04L12/56
摘要： PURPOSE:To secure continuity of information by controlling storage of consecutive media with a frame rate using an identifier so as to prevent overflow or underflow of a buffer. CONSTITUTION:Overflow or underflow of a buffer 108 of a decoder 110 is prevented and an identifier is provided to each frame and the result is stored to secure consecutive information. When an error is confirmed in a frame giving much effect onto other frame, a control unit 104 requests retransmission of the frame to a server 101 and stops a screen output tentatively till the frame reaches the decoder 110 of a client 102. Furthermore, priority of a frame giving much effect on other frames is placed high at communication. When a request of special reproduction comes from the client 2, a comparator 105 of the server 101 reads a frame selectively and sends the frame to the client 102.

10. 发明专利

JPH0340620A SLOT ACCESS SYSTEM 失效
公开(公告)号：JPH0340620A
公开(公告)日：1991-02-21
申请号：JP17401689
申请日：1989-07-07
申请人： HITACHI LTD
发明人： TAKIYASU YOSHIHIRO , AMADA EIICHI , SHIGESA HIDEHIKO , KOBAYASHI NAOYA , YAMAGA MITSUHIRO , HIYAMA KUNIO , TAKADA OSAMU
IPC分类号： H04L12/42
摘要： PURPOSE:To attain throughput whose value is '1' or over without causing impartial provision of access right by adopting a system that a reception node releases a slot, supervising the occurrence of an impartial access, and employing the system that a transmission node releases the slot when the access is judged as impartial. CONSTITUTION:A transmission node (S1)41 acquires a slot access right by setting information to a received idle slot (((B bit), (R bit))=(0,0)) to revise a header content into (1, 0). A reception node (D) 42 copies the content of the said slot, and sets the content to (0, 0) to release the slot access right. A transmission node (S2) 43 can acquire the released slot access right. An acquisition request node (R)44 unable to acquire the access right for a long time having information to be sent applies acquisition request of the access right to the transmission node (S1)41 by revising the content to (1, 1).

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