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1. 发明专利

JPS5877328A CMOS INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS5877328A
公开(公告)日：1983-05-10
申请号：JP17458981
申请日：1981-11-02
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAHASHI YOSHIKAZU , KITAMURA NOBUAKI , TAKECHI MAKOTO
IPC分类号： H01L21/8238 , H01L21/82 , H01L27/092 , H01L27/118 , H03K19/0948 , H03K19/173
摘要： PURPOSE:To perform sufficient aging, by providing a tri-state circuit selectively applying the logical level for aging to an external input terminal. CONSTITUTION:An input signal is inputted to a logical circuit block through an input buffer circuit IB from a terminal IN1-INl. An output signal formed at a logical circuit block LOG through an output buffer circuit OB is outputted from terminals OUT1-OUTm. Terminals IO1-IOn are provided with an input/output buffer circuit TOB comprising a tri-state output buffer circuit TOB and input buffer circuit IB and are used for input and output terminals to a logical circuit block LOG.

2. 发明专利

JPS57211248A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS57211248A
公开(公告)日：1982-12-25
申请号：JP9535781
申请日：1981-06-22
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAHASHI YOSHIKAZU , ITOU TSUNEO , TAKECHI MAKOTO
IPC分类号： H01L21/822 , H01L21/60 , H01L21/82 , H01L27/04 , H01L27/118 , H03K19/003 , H03K19/0185 , H03K19/173
摘要： PURPOSE:To contrive to enlarge the degree of freedom of design of a master slice type IC by a method wherein the pad providing region adjoining to an I/O cell is divided into the plural number, and isolated and independent pads are provided respectively thereto. CONSTITUTION:When Al wirings 19 for independence of function of an input protective circuit (resistros 12 and diodes 14), an input circuit 15 and a CMOS inverter circuit 16 are to be provided in the I/O cell 5 conformed to the fundamental design, pads 6a-1, 6b-1 of the first layer Al-Ifor leading out of input-output independently from the cell of one piece are also provided and are connected 19. The second layer Al-II is provided interposing an insulating layer between them. Connection between the fundamental cell 2 and the I/O cell 5, an electric power source VDD, earthing wirings are provided, Al pads 6a-2, 6b-2 are accumulated directly upon the pads, and when the upper side and lower side Al layers are connected at the place shown with the ? mark, the pads 6a-1, 6a-2 for input and the pads 6b-1, 6b-2 for output are formed being isolated mutually adjoining to the I/O cell. The IC enabled to select voluntarily both of input- output and independent input or output can be obtained from the I/O cell of one piece using the pads of the plural number having constitution mentioned above.

3. 发明专利

JPS5992538A DIGITAL SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS5992538A
公开(公告)日：1984-05-28
申请号：JP20212982
申请日：1982-11-19
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MORI KAZUTAKA , TAKAHASHI YOSHIKAZU
IPC分类号： H01L21/822 , H01L21/60 , H01L21/607 , H01L27/04
摘要： PURPOSE:To augment the integration of the titled device by a method wherein input and output circuits and bonding pads are intentionally matched. CONSTITUTION:The bonding pads P1, P2 at ends are formed into diamond shape corresponding to the connecting line in the wiring direction for supersonic bonding. At the same time, the central pads Pi, Pi+1 etc. are formed into square shape corresponding to the direction of the connecting line. The distance between adjoining pads at the end and the central part may be differentiated from each other by means of differentiating the shapes of the pad P at the end and the central part. Therefore, the pads P1, P2 at the ends are allocated to the terminals for the input/output circuit I/O with relatively larger occupation area while the pads at the central part are allocated to the terminals for the exclusive output circuit OB or the exclusive input circuit IB with relatively smaller occupation area. Through these procedures, the matching between pads and input/output circuits may be improved to augment the integration eliminating the needless space.

4. 发明专利

JPS57210729A LOGICAL INTEGRATED CIRCUIT 失效
公开(公告)号：JPS57210729A
公开(公告)日：1982-12-24
申请号：JP9535581
申请日：1981-06-22
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAHASHI YOSHIKAZU , TAKECHI MAKOTO , MURATA SHINGO
IPC分类号： G11C11/407 , H01L21/822 , H01L27/04 , H03K19/00
摘要： PURPOSE:To perform stable operation even if an output circuit charges or discharges a lot of external capacitors, by independently providing a power supply system energizing an input circuit and an internal circuit and a power supply system energizing an output circuit, in an MOS logical integrated circuit. CONSTITUTION:A CMOS integrated circuit is formed on a single semiconductor chip 10 and has input buffers 12-1-12-m, an internal circuit 14, and output buffers 16-1-16-n. The buffers 12-1-m are connected to input terminals 20-1-m and the output is connected to the circuit 14. The buffers 16-1-n are connected to the circuit 14 and the output is connected to terminals 28-1-n. A battery Vdd1 is connected to the buffers 16-1-n via a power terminal 32 and the other terminals are connected to a ground terminal 36. A power supply VDD2 is connected to the buffers 12-1-m and the circuit 14 and the other terminals are connected to a ground terminal 46. Thus, even if the potential at the terminals 32 and 36 is fluctuated with charge/discharge of external capacitors C1-Cn, no fluctuation is given to the threshold value receiving the input signal of the buffers 12-1-n.

5. 发明专利

JPS58101438A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS58101438A
公开(公告)日：1983-06-16
申请号：JP19859381
申请日：1981-12-11
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAHASHI YOSHIKAZU , SATOU YASUO
IPC分类号： H01L27/04 , H01L21/3205 , H01L21/82 , H01L21/822 , H01L23/52 , H01L23/64 , H01L27/118
摘要： PURPOSE:To eliminate the adverse influences of the external floating capacity and the inductance of lead wirings affected to a semiconductor integrated circuit device by respectively providing independently isolated load resistances between a plurality of output buffers in an IC and bonding pads. CONSTITUTION:A polysilicon resistor 10 is formed in advance together with other IC forming element on an Si pellet 2 between elements forming output buffers 7a-7n and bonding pads 9. In order to obtain an IC in which a circuit 8 performs the prescribed logic operation and the buffers 7a-7n instantaneously output, the influences of external floating capacity C and the inductance L of lead wirings 3 are small. Accordingly, the buffers are shortcircuited with the pads via wirings 11. On the other hand, in order to output signals of large number of bits from the buffers 7 in parallel with each other, the resistor 10 is inserted between the buffers and the pads 9, thereby reducing the transient current of charging and discharging the C and preventing the induction of noise and the fluctuation of the level of the output signal by a power source or grounding wirings.

6. 发明专利

JPS5851538A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS5851538A
公开(公告)日：1983-03-26
申请号：JP14946381
申请日：1981-09-24
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAHASHI YOSHIKAZU , TAKECHI MAKOTO
IPC分类号： H01L21/822 , H01L21/3205 , H01L21/82 , H01L23/52 , H01L27/04 , H01L27/118
摘要： PURPOSE:To enable to facilitate the addition of wirings in a semiconductor integrated circuit device by forming a conductive layer which extends directly under upper layer wirings forming power source reinforcing lines and using the layer as wirings, thereby increasing the number of wiring channels. CONSTITUTION:A plurality of polysilicon wirings 13, 14 are respectively formed in the same directions (perpendicular to each cell row) directly under power source reinforcing lines 5, 6, and are suitably connected at the prescribed positions to the first layer aluminum wirings 15 of a wiring channel region 4. In this manner, it becomes equivalent to the increase in the number of the second layer aluminum wirings in the amount corresponding to the wirings 13, 14. Accordingly, the number of logic gates can be increased by increasing the number of wirings in the direction perpendicular to the cell row and increasing the number of wirings running in the wiring channel region.

7. 发明专利

JPS5882533A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS5882533A
公开(公告)日：1983-05-18
申请号：JP10706281
申请日：1981-07-10
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAHASHI YOSHIKAZU
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H01L27/10 , H01L27/118
摘要： PURPOSE:To reduce excess area of wiring region by alternately configurating the unit cell lines for logic circuits and the memory cell lines for storage element, and by forming the peripheral circuits of memory with the unit cell lines and the memory cells with the cell lines at the time of arrangement. CONSTITUTION:The unit cell lines for configurating logic circuits is composed of the repeated gate arrays in unit of CMOS, including a P layer 9 of FET, N layer 10, poly Si gate electrode 11 between these layers and connecting hole for bias. The memory cell lines are also composed of the repeated arrays in unit of CMOS, including a P layer 13, N layer 14 and poly Si gate electrode 15. (P well is not shown in the figure) On the occasion of arrangement, the cells 2, 3 are wired by Al leads 16, 17 and connected to the diffusion layer or gate electrode on each unit, extending in lateral within the specified region of a wiring region 4. The wiring 16' and power source wiring of the diffusion layer and region 3 are considered as the second wiring layer. A NOR gate is formed in the line 2, for example, by the wirings 16, 17, while an inverter in the line 3. According to this structure, the region between lines 4 is effective used and a compact multi-function SLI can be formed.

8. 发明专利

JPS57211076A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS57211076A
公开(公告)日：1982-12-24
申请号：JP9535681
申请日：1981-06-22
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAHASHI YOSHIKAZU
IPC分类号： G01R31/28
摘要： PURPOSE:To set easily the output voltage at a desired level, by separating an output circuit from an internal logical circuit with an external control signal and applying other external signals to the output circuit. CONSTITUTION:A high level of control voltage is applied to a pad 4 to perform a test of the output circuits 7-1-7-n. In this case, a control line 9 is set at a high level, and a control line 9-1 is set at a low level by an inverter 21. Then the MOSFET20-3 and 20-4 are turned on with 20-1 and 20-2 turned off respectively. Thus a control line 8 is connectd to the input terminal of an output terminal 7-1 via a circuit 30-1. As a result, both the output voltage and output current levels can be tested for the circuits 7-1-7-n based on the control signal applied to a pad 3 not by the output signal of an internal logical circuit 2.

9. 发明专利

JPS6039705A ALUMINUM STABILIZED SUPERCONDUCTIVE CONDUCTOR 失效
公开(公告)号：JPS6039705A
公开(公告)日：1985-03-01
申请号：JP14811683
申请日：1983-08-15
申请人： JAPAN ATOMIC ENERGY RES INST , HITACHI LTD
发明人： ANDOU TOSHINARI , TAKAHASHI YOSHIKAZU , NISHI MASATAKA , SHIMAMOTO SUSUMU , AIHARA KATSUZOU , TADA NAOFUMI
IPC分类号： H01B13/00 , H01B12/10 , H01L39/14

10. 发明专利

JPS5782950A Direct heated color braun tube 失效
标题翻译：直接加热颜色布朗管
公开(公告)号：JPS5782950A
公开(公告)日：1982-05-24
申请号：JP15828580
申请日：1980-11-12
申请人： Hitachi Ltd
发明人： TAKAHASHI YOSHIKAZU
IPC分类号： H01J29/90
CPC分类号： H01J29/90
摘要： PURPOSE:To restrain the influence of contact resistance between a stem outer lead and a socket pin, by arranging a soft lead on the stem outer lead for connecting a heater of a CRT and connecting electrically the soft lead to the terminal of a socket base. CONSTITUTION:In the end portion of the next tube 4(a) of a CRT4, a soft lead 6 is arranged on a stem outer lead 5 connected to a heater lead 2, interposing an inner lead 14 and a wire 13, among stem outer leads connected to inside electrodes. The lead 5 is contacted with and connected to the socket pin 8 of a socket 7 by drawing the lead 6 out from the back side of the socket 7 through the pin 8, and the lead 6 is directly connected by melting to the terminal 10 on a socket base 9 arranged closely on the back surface of the socket 7, that is, the terminal 10 to which the pin 8 is connected electrically, by solder 11. Thereby, contact resistance between the lead 5 and the pin 8 becomes zero, and the variation of contact resistance between cathodes can be made to be nil.
摘要翻译：目的：为了限制杆外引线和插座针之间的接触电阻的影响，通过在杆外引线上设置软引线来连接CRT的加热器，并将软引线电连接到插座底座的端子。构成：在CRT4的下一个管4（a）的端部，软引线6布置在连接到加热器引线2的杆外引线5上，插入内引线14和导线13，杆管外引线引线连接到内部电极。引线5通过引脚8从插座7的后侧拉出引线6并通过熔丝直接连接到端子10上而与插座7的插座销8接触并连接插座底座9紧密地布置在插座7的后表面上，即通过焊料11将引脚8电连接到的端子10.由此，引线5和引脚8之间的接触电阻变为零，并且可以使阴极之间的接触电阻的变化为零。

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