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1. 发明专利

JPS57210729A LOGICAL INTEGRATED CIRCUIT 失效
公开(公告)号：JPS57210729A
公开(公告)日：1982-12-24
申请号：JP9535581
申请日：1981-06-22
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAHASHI YOSHIKAZU , TAKECHI MAKOTO , MURATA SHINGO
IPC分类号： G11C11/407 , H01L21/822 , H01L27/04 , H03K19/00
摘要： PURPOSE:To perform stable operation even if an output circuit charges or discharges a lot of external capacitors, by independently providing a power supply system energizing an input circuit and an internal circuit and a power supply system energizing an output circuit, in an MOS logical integrated circuit. CONSTITUTION:A CMOS integrated circuit is formed on a single semiconductor chip 10 and has input buffers 12-1-12-m, an internal circuit 14, and output buffers 16-1-16-n. The buffers 12-1-m are connected to input terminals 20-1-m and the output is connected to the circuit 14. The buffers 16-1-n are connected to the circuit 14 and the output is connected to terminals 28-1-n. A battery Vdd1 is connected to the buffers 16-1-n via a power terminal 32 and the other terminals are connected to a ground terminal 36. A power supply VDD2 is connected to the buffers 12-1-m and the circuit 14 and the other terminals are connected to a ground terminal 46. Thus, even if the potential at the terminals 32 and 36 is fluctuated with charge/discharge of external capacitors C1-Cn, no fluctuation is given to the threshold value receiving the input signal of the buffers 12-1-n.

2. 发明专利

JPS5877328A CMOS INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS5877328A
公开(公告)日：1983-05-10
申请号：JP17458981
申请日：1981-11-02
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAHASHI YOSHIKAZU , KITAMURA NOBUAKI , TAKECHI MAKOTO
IPC分类号： H01L21/8238 , H01L21/82 , H01L27/092 , H01L27/118 , H03K19/0948 , H03K19/173
摘要： PURPOSE:To perform sufficient aging, by providing a tri-state circuit selectively applying the logical level for aging to an external input terminal. CONSTITUTION:An input signal is inputted to a logical circuit block through an input buffer circuit IB from a terminal IN1-INl. An output signal formed at a logical circuit block LOG through an output buffer circuit OB is outputted from terminals OUT1-OUTm. Terminals IO1-IOn are provided with an input/output buffer circuit TOB comprising a tri-state output buffer circuit TOB and input buffer circuit IB and are used for input and output terminals to a logical circuit block LOG.

3. 发明专利

JPS57211248A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS57211248A
公开(公告)日：1982-12-25
申请号：JP9535781
申请日：1981-06-22
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAHASHI YOSHIKAZU , ITOU TSUNEO , TAKECHI MAKOTO
IPC分类号： H01L21/822 , H01L21/60 , H01L21/82 , H01L27/04 , H01L27/118 , H03K19/003 , H03K19/0185 , H03K19/173
摘要： PURPOSE:To contrive to enlarge the degree of freedom of design of a master slice type IC by a method wherein the pad providing region adjoining to an I/O cell is divided into the plural number, and isolated and independent pads are provided respectively thereto. CONSTITUTION:When Al wirings 19 for independence of function of an input protective circuit (resistros 12 and diodes 14), an input circuit 15 and a CMOS inverter circuit 16 are to be provided in the I/O cell 5 conformed to the fundamental design, pads 6a-1, 6b-1 of the first layer Al-Ifor leading out of input-output independently from the cell of one piece are also provided and are connected 19. The second layer Al-II is provided interposing an insulating layer between them. Connection between the fundamental cell 2 and the I/O cell 5, an electric power source VDD, earthing wirings are provided, Al pads 6a-2, 6b-2 are accumulated directly upon the pads, and when the upper side and lower side Al layers are connected at the place shown with the ? mark, the pads 6a-1, 6a-2 for input and the pads 6b-1, 6b-2 for output are formed being isolated mutually adjoining to the I/O cell. The IC enabled to select voluntarily both of input- output and independent input or output can be obtained from the I/O cell of one piece using the pads of the plural number having constitution mentioned above.

4. 发明专利

JPS5851538A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS5851538A
公开(公告)日：1983-03-26
申请号：JP14946381
申请日：1981-09-24
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAHASHI YOSHIKAZU , TAKECHI MAKOTO
IPC分类号： H01L21/822 , H01L21/3205 , H01L21/82 , H01L23/52 , H01L27/04 , H01L27/118
摘要： PURPOSE:To enable to facilitate the addition of wirings in a semiconductor integrated circuit device by forming a conductive layer which extends directly under upper layer wirings forming power source reinforcing lines and using the layer as wirings, thereby increasing the number of wiring channels. CONSTITUTION:A plurality of polysilicon wirings 13, 14 are respectively formed in the same directions (perpendicular to each cell row) directly under power source reinforcing lines 5, 6, and are suitably connected at the prescribed positions to the first layer aluminum wirings 15 of a wiring channel region 4. In this manner, it becomes equivalent to the increase in the number of the second layer aluminum wirings in the amount corresponding to the wirings 13, 14. Accordingly, the number of logic gates can be increased by increasing the number of wirings in the direction perpendicular to the cell row and increasing the number of wirings running in the wiring channel region.

5. 发明专利

JPH0479144B2 失效
公开(公告)号：JPH0479144B2
公开(公告)日：1992-12-15
申请号：JP5508383
申请日：1983-04-01
申请人： HITACHI LTD
发明人： SATO YASUO , TAKECHI MAKOTO
IPC分类号： H01L21/3205 , H01L21/82 , H01L23/52 , H01L27/10 , H01L27/118

6. 发明专利

JPS62128148A MASTER SLICE TYPE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62128148A
公开(公告)日：1987-06-10
申请号：JP26716685
申请日：1985-11-29
申请人： HITACHI LTD
发明人： KUBOKI SHIGEO , MEJIRO TETSUO , TAKAHASHI TOSHIO , TAKECHI MAKOTO
IPC分类号： H01L27/092 , H01L21/82 , H01L21/8238 , H01L21/8246 , H01L27/08 , H01L27/10 , H01L27/112 , H01L27/118
摘要： PURPOSE:To simplify a wiring work as well as to form a ROM macro-cell of small size and low power consumption by a method wherein the source electrodes of PMOS and NMOS transistors are connected to a power source line and a grounding line, a drain electrode is connected to a bit line, a gate electrode is connected to the word wires of a negative logic and positive logic using a wiring layer, and 1 and 0 are wrote in respectively. CONSTITUTION:The bit cells 76-91 of PMOS and NMOS transistor pair are present at the position where the word line pairs 92, 92'-95 and bit line groups 96-99, to be connected to the inverters 100-103 for inversion of a word address signal, intersect one another. When a word line is formed with AL1, a bit line is formed with AL2, and the gate electrode of a transistor pair intersects with the word line on a poly Si film SD. When a 0 or a 1 is going to be wrote in, the gate electrode of the NMOS or the PMOS transistor is connected to a positive logical or a negative logical word address signal lines 92'-95' or 92-95 by providing contact holes CONT on a poly-Si film. Then, an unused electrode is connected to a power source line VDD1 or a grounding line VSS1, and the MOS is brought into a cut-off state.

7. 发明专利

JPS6028241A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6028241A
公开(公告)日：1985-02-13
申请号：JP13580883
申请日：1983-07-27
申请人： HITACHI LTD
发明人： TAKECHI MAKOTO
IPC分类号： H01L21/822 , H01L21/82 , H01L23/528 , H01L27/04 , H01L27/118
摘要： PURPOSE:To form a wiring easily while obtaining the optimum arrangement by fitting terminals to the intermediate sections of a plurality of fundamental cell rows and input-output cells and bending and forming the wiring through said terminals when the fundamental cell rows are mounted to the central section of a semiconductor substrate and the input-output cells to the peripheral section of the substrate and the cell rows and the cells are connected mutually by using the wiring. CONSTITUTION:A plurality of fundamental cell rows 3 are respectively formed to the central section of a semiconductor substrate 1 while holding channel regions 4, input-output buffers 2 connected to the cell rows are fitted to the peripheral section of the substrate 1, and bonding pads 5 are connected to the cell rows and the buffers. The cell rows 3 and the buffers 2 are connected by lateral first layer Al wirings 8 crossing each channel region 4 and vertical second layer Al wirings 9, but a plurality of terminals 7 are formed previously among the cell rows and the buffers, and the cell rows and the buffers are each connected through the terminals. Accordingly, wiring inhibiting regions among the end sections of the cell rows 3 and the end sections of the buffers 2 are reduced, and the degree of freedom of the wirings is improved.

8. 发明专利

JPS59132144A Manufacture of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造
公开(公告)号：JPS59132144A
公开(公告)日：1984-07-30
申请号：JP590783
申请日：1983-01-19
申请人： Hitachi Ltd
发明人： YUYAMA YASUSHI , TAKECHI MAKOTO
IPC分类号： H01L21/822 , H01L21/82 , H01L27/02 , H01L27/04 , H01L27/118
CPC分类号： H01L27/0207
摘要： PURPOSE:To shorten and facilitate the wiring between variable length cells, by providing an arrangement improving process, by which the variable length cells are exchanged and arranged when the areas of the cells are different. CONSTITUTION:The areas of all variable length cells other than basic variable length cell are the integer times the area of the variable length cell. The variable length cell 3B has the area twice the basic variable length cell 3A. The variable length cell 3A and a variable length cell 3C in the vicinity thereof are combined so that the area becomes equal to the area of the variable cell 3B. The variable length cells 3A and 3B are exchanged and arranged. In this way, the restriction of the arranging pattern of the variable length cells can be eased, and the wiring between the variable length cells is shortened and facilitated.
摘要翻译：目的：通过提供一种布置改进过程来缩短和促进可变长度单元之间的布线，当单元的区域不同时，通过该布置改进处理可变长度单元被交换和排列。构成：基本可变长度单元以外的所有可变长度单元格的区域是可变长度单元格区域的整数倍。可变长度单元3B具有两倍于基本可变长度单元3A的面积。可变长度单元3A和其附近的可变长度单元3C组合，使得该面积变得等于可变单元3B的面积。可变长度单元3A和3B被交换和布置。以这种方式，可以减轻可变长度单元的布置图案的限制，并且可缩短并简化可变长度单元之间的布线。

9. 发明专利

JPS5956762A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS5956762A
公开(公告)日：1984-04-02
申请号：JP15328283
申请日：1983-08-24
申请人： Hitachi Ltd
发明人： TAKECHI MAKOTO , KAWAMOTO HIROSHI
IPC分类号： H01L27/10 , H01L21/8234 , H01L21/8242 , H01L23/522 , H01L27/06 , H01L27/108 , H01L29/78
CPC分类号： H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： PURPOSE:To contrive to improve the flexibility of wiring design and the integration degree by a method wherein the second wiring layer is enabled to be easily connected directly to a source layer and a drain layer by thinning the film thickness of an interlayer insulation film. CONSTITUTION:Si oxide films 2 are formed on a P type Si substrate 1. P type Si layer 3 are formed under the oxide films 2. The source layer 4 and the drain layer 5 are formed by the selective diffusion of an N type impurity, a polycrystalline Si layer 7, a gate electrode, covered with an Si thermal oxide film 6 is provided on the surface of the Si substrate 1 therebetween, and accordingly an Si gate MOS transistor 8 is formed. Polycrystalline Si layers 9 and 10 serving as the first wiring layer are formed on the upper surface of the Si oxide films 2. A polycrystalline Si layer 13 serving as the second wiring layer is formed on an Si thermal oxide film 12 serving as the layer insulation film. The source layer 4 and the drain layer 14 are connected directly to the wiring layer of a polycrystalline Si layer formed simultaneously with the polycrystalline Si layer 13.
摘要翻译：目的：为了通过使层间绝缘膜的膜厚变薄，能够容易地将第二布线层直接连接到源极层和漏极层的方法来提高布线设计的灵活性和集成度。构成：在P型Si衬底1上形成Si氧化物膜2.在氧化物膜2的下方形成P +型Si层3.源极层4和漏极层5通过选择性扩散N形成 <+>型杂质，在Si衬底1的表面上设置多晶Si层7，覆盖有Si热氧化膜6的栅极，因此形成Si栅极MOS晶体管8。在Si氧化膜2的上表面上形成用作第一布线层的多晶硅层9和10.作为第二布线层的多晶Si层13形成在作为层绝缘体的Si热氧化膜12上电影。源极层4和漏极层14直接连接到与多晶Si层13同时形成的多晶Si层的布线层。

10. 发明专利

JPS63239841A GATE ARRAY LOGIC DESIGNING SYSTEM AND GATE ARRAY THEREOF 失效
公开(公告)号：JPS63239841A
公开(公告)日：1988-10-05
申请号：JP7142387
申请日：1987-03-27
申请人： HITACHI LTD
发明人： TAKECHI MAKOTO
IPC分类号： H01L27/118 , H01L21/82 , H03K19/173
摘要： PURPOSE:To easily perform a logic design and a circuit design without sacrificing an operating speed by composing a logic circuit having a specific circuit function in a library by the combination of a plurality of basic cells disposed to hole a wiring channel. CONSTITUTION:NAND gates for forming output signals G to F are composed of basic cells G5 to G8 disposed in parallel in a downward column to hold a wiring channel in between. The cells G5 to G8 are formed of 3-input NAND gates. The cells G1 to G4 and G5 to G8 are connected by contact holes for connecting first and second layer wirings at positions formed with a first layer aluminum wiring layer designated by broken lines, a second layer aluminum wiring layer designated by solid lines and marked with 'x'. A logic circuit in a library is provided similarly to a hard micro to have the specific circuit function to handle the logic circuit having the prepared circuit function as it is as a black box to realize the desired logic function.

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