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1. 发明专利

JPH02277339A RING LAN SYSTEM 失效
公开(公告)号：JPH02277339A
公开(公告)日：1990-11-13
申请号：JP9746989
申请日：1989-04-19
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： NAKAYAMA HARUYUKI , SUKEGAWA FUMIO , NAKAMURA KAZUNORI
IPC分类号： H04L12/42
摘要： PURPOSE:To improve the throughput among user equipments of packet switching system information by using a master node equipment to apply transmission control so that a ring circulation delay of packet switching system information is a value in response to a traffic unit of packet switching system information in a ring. CONSTITUTION:A delay is applied to a slot 61 of line switching system information to insert the slot 61 to a fixed location in a line switching system information transmission area 71 and no delay is applied to a slot of packet switching system information to be relayed but relayed as soon as possible. The delay in the slot of the packet switching system information is varied with a number of slots subject to buffering in a packet switching system information relay buffer, that is, a traffic of the packet switching system information. When the delay in the relay of the packet switching system information is minimum, only the ring transmission delay and the in-node processing delay exist and the throughput of the packet switching system information between user node equipments is improved.

2. 发明专利

JPS6462042A CLOCK SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPS6462042A
公开(公告)日：1989-03-08
申请号：JP21933287
申请日：1987-09-02
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KINOSHITA MASASHI , MASUDA TAKASHI , SUKEGAWA FUMIO
IPC分类号： H04L7/00
摘要： PURPOSE:To supply a high speed synchronizing clock signal to a system independently of an input clock signal by using a characteristic of a PLL circuit capable of outputting even when no input clock signal exists as a 1st synchronizing part and using an LC circuit capable of high speed oscillation as a 2nd synchronizing part. CONSTITUTION:A pre-stage PLL circuit 1 as the 1st circuit section and a post- stage synchronizing circuit 2 as the 2nd circuit section are connected in series. The output of the pre-stage PLL circuit 1 is given to the post-stage synchronizing circuit 2 and branched and fed back to the pre-stage PLL circuit 1 via a frequency divider 3. Since the phase synchronizing feedback circuit such as the PLL circuit 1 or the like in the 1st synchronizing part is capable of being run itself, even when the input system is separated and the input clock signal is interrupted, the output clock signal is supplied to the system. Moreover, the element or circuit coping with the high speed is adopted for the 2nd synchronizing section, the synchronizing is attained even to a high speed clock signal. Thus, a high speed synchronizing clock signal is supplied to the system.

3. 发明专利

JPH04150634A MULTI-CONNECTION LINE CONTROL SYSTEM 失效
公开(公告)号：JPH04150634A
公开(公告)日：1992-05-25
申请号：JP27333090
申请日：1990-10-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MOTOKI YOSHIKO , MORITA TAKASHI , WADA KOJI , SUKEGAWA FUMIO , SUGAWARA TAKASHI
IPC分类号： H04L12/28
摘要： PURPOSE:To allow the system to cope with revision or movement of each terminal equipment with modification of inside of an intermediate connection function only by using the intermediate connection function accommodating one each of lines at a center equipment and a terminal equipment and managing connection centralizingly so as to attain multi-connection. CONSTITUTION:The system consists of a host CPU 1, a host CPU use line controller 2, transmission lines 21,22,90-93, line accommodation equipments 30,31,50-53, connector 4, 60-63, terminal equipments 70-73 and a connection controller 8. A center equipment sends a same data in a broadcast way to each of terminal equipments in multi-connection, while the communication from each of the terminal equipments to the center equipment is implemented by allowing a terminal equipment sending a transmission request to occupy a transmission line from the terminal equipment to the center equipment based on the intermediate connection function or a detection function for a transmission request provided around the intermediate connection function. Thus, any wiring work is not required for the movement or replacement of a terminal equipment.

4. 发明专利

JPH02257733A LOOP TRANSMISSION SYSTEM 失效
公开(公告)号：JPH02257733A
公开(公告)日：1990-10-18
申请号：JP7666289
申请日：1989-03-30
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： NAKAMURA KAZUNORI , SUKEGAWA FUMIO , NAKAYAMA HARUYUKI
IPC分类号： H04L12/42
摘要： PURPOSE:To eliminate the need for the limit of node number due to alignment jitter by devising a system such that the number of node equipments pulling-in a data from a same system in a closed loop by loopback connection does not exceed continuously a prescribed number (n) determined in advance. CONSTITUTION:The system is provided with a reception section 10 receiving a signal from active and reserve system transmission lines, a transmission section 12 sending a signal to the transmission line of the active and reserve system, a control section 13, a SW section 11 applying the selection control of a data and a clock based on an instruction from the control section 13 and an oscillator 14 for internal clock. Plural node equipments 1-6 are connected to the active and reserve system loop transmission lines. Then the system is so devised that the number of node equipments pulling-in the data from a same system does not exceed continuously the prescribed number (n) determined in advance, in a closed loop formed by a loopback connection. Thus, the limit of the node number by alignment jitter is eliminated.

5. 发明专利

JPH1165893A WATCHDOG TIME-OUT DETECTION TIME RESET SYSTEM 失效
公开(公告)号：JPH1165893A
公开(公告)日：1999-03-09
申请号：JP22772997
申请日：1997-08-25
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： MATSUNO TAKASHI , ABE SUSUMU , OYA YOICHI , SUKEGAWA FUMIO , SAKAGUCHI YASUHIRO
IPC分类号： G06F11/30
摘要： PROBLEM TO BE SOLVED: To obtain a circuit which can easily set an arbitrary wait time by allowing a watchdog timer to perform watchdog time-out detection and wait time setting up to hardware resetting after the watchdog time-out detection. SOLUTION: A watchdog time-out value is set in a watchdog time-out value setting circuit 10 and a wait time up to hardware reset issue after watchdog time-out detection is set in a hardware reset wait value setting circuit 11 respectively. A watchdog time-out value/hardware reset wait value selecting circuit 12 selects the value from the watchdog time-out value setting circuit 10 when a watchdog time-out detection signal 101 is negated and the value from the hardware reset value setting circuit 11 when the asserted respectively and sends it out to a time-out detecting circuit 13.

6. 发明专利

JPH08149456A CAMERA SWITCHOVER SYSTEM 失效
公开(公告)号：JPH08149456A
公开(公告)日：1996-06-07
申请号：JP28167694
申请日：1994-11-16
申请人： HITACHI LTD
发明人： OYA YOICHI , SUKEGAWA FUMIO
IPC分类号： H04N7/18 , H04L12/42
摘要： PURPOSE: To obtain a camera switchover system which is effective for switching the images of the plural cameras connected with nodes and displaying the image on a monitor, in a loop LAN. CONSTITUTION: In the loop LAN which is composed of plural nodes 21 to 24 and a transmission line 1 connecting the nodes on a loop, connects each node with a monitor 6, plural camera switch controllers 31 to 39 and cameras 41 to 49 and switches the images of the cameras by the instruction from a monitor side, output node information and output camera information are provided in a transmission frame revolving around the transmission line 1. The switchings of the images of the plural cameras to be connected with the loop LAN can be realized by a simple H/W constitution, and also the confirmation of a switch operation as to whether the outputs to the loop of the images from the nodes are rightly performed or not can be realized.

7. 发明专利

JPS6464436A COMMUNICATION SYSTEM 失效
公开(公告)号：JPS6464436A
公开(公告)日：1989-03-10
申请号：JP22048387
申请日：1987-09-04
申请人： HITACHI LTD
发明人： SUKEGAWA FUMIO
摘要： PURPOSE:To improve the utilizing efficiency of a time slot and to obtain efficient activity by adding information to identify the receiving opponent of data loaded on a time slot group into the time slot. CONSTITUTION:A signal frame is formed by the time slot for synchronizing and the plural time slots for data and divided into the plural time slot groups for data. As receiving opponent identifying information to show wether the data to be loaded on the time slot group are the data from a master station to a slave station or the data from the slave station to the master station, the two act bits of an ACTM bit to show to be the data from the master station and an ACTS bit to show to be the data from the slave station are added. Thus, the utilizing efficiency of the time slot can be improved.

8. 发明专利

JPS6264150A TIME DIVISION MULTIPLEX TRANSMITTER 失效
公开(公告)号：JPS6264150A
公开(公告)日：1987-03-23
申请号：JP20326785
申请日：1985-09-17
申请人： HITACHI LTD
发明人： SUKEGAWA FUMIO
摘要： PURPOSE:To improve the utilizing efficiency of a time slot by adding the information representing an opposite transmitter received to each time slot so as to apply data exchange in one time slot per line. CONSTITUTION:A data received by an interface control circuit 31 is stored in a transmission buffer temporarily, a value of a reception control bit designation register 28 is added as a reception control bit by a reception control bit addition circuit 27, inserted in a time slot designated by a time slot designation register 25 by a time slot selection circuit 24 and sent to a loop transmission line 1 via a frame detection circuit 23 and a transmission circuit 22. On the other hand, a frame circulating through the transmission line 1 is subject to frame synchronization detection, decomposed at each time slot by the circuit 23 and a data of the time slot designated by the register 25 is selected by the circuit 24 and only when the reception control bit included in the time slot is coincident with the complement of the value in the register 28, the data is inserted to a reception buffer 29 from a reception control bit check circuit 26 and sent via the circuit 31.

9. 发明专利

JP2000278261A ISDN CONNECTION DEVICE 失效
公开(公告)号：JP2000278261A
公开(公告)日：2000-10-06
申请号：JP8539099
申请日：1999-03-29
申请人： HITACHI LTD
发明人： SUKEGAWA FUMIO , SHIRAISHI TSUTOMU , KAMENO HIDEJI
IPC分类号： H03L7/10 , H04L1/22 , H04L7/033 , H04L12/02 , H04M11/00 , H04Q11/04
摘要： PROBLEM TO BE SOLVED: To prevent disturbance in an output clock at the switching of an input clock of a PLL to generate a multiplex clock in a clock changeover control circuit of an ISDN connection device. SOLUTION: The ISDN connection device comprising a plurality of ISDN interface circuits (ISDN i/f0-n) 4-0-4-n, a channel data transmission reception section that controls transmission reception of data multiplexed on a channel, a PLL (1-2) to take synchronization of a clock and a clock changeover control circuit 1, multiplexing data of a plurality of the ISDN interface circuits (ISDN i/f0-n) 4-0-4-n by using a high speed clock synchronously with an ISDN and giving the result to the channel data transmission reception section 3 that applies transmission reception processing to the data in a lot is configured such that two frequency dividers (frequency divider A) for a system A and (frequency divider B) for a system B of a PLL are provided to the clock changeover control circuit, and a circuit selecting sequentially a clock for phase matching for an active/standby system is provided.

10. 发明专利

JPH0715457A DIGITAL COMMUNICATION SWITCHOVER SYSTEM 失效
公开(公告)号：JPH0715457A
公开(公告)日：1995-01-17
申请号：JP14744193
申请日：1993-06-18
申请人： HITACHI LTD , HITACHI COMPUTER ELECTRONIC
发明人： SUKEGAWA FUMIO , FURUSAWA TAKESHI , SUGIMOTO FUMINORI , OYA YOICHI
IPC分类号： H04N5/232 , H04L12/42
摘要： PURPOSE:To provide an effective digital communication switchover system to switch over pictures of plural cameras connecting to a node and to display the picture onto a monitor in a loop LAN. CONSTITUTION:A loop LAN which is made up of plural odes 2A-2D and a transmission line 1 connecting them as a loop and in which a monitor 3 and plural cameras 61-63 are connected to each node and the picture of the cameras is switched over by a command from the monitor is provided with output command information, picture synchronizing signal information and replay monitor information in a transmission frame circulated through the transmission line 1. Thus, the changeover of the plural cameras 61-63 is realized with simple hardware configuration and disturbance of the picture at the time of switch over is prevented and abnormal picture data are monitored.

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