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1. 发明专利

JPH1165893A WATCHDOG TIME-OUT DETECTION TIME RESET SYSTEM 失效
公开(公告)号：JPH1165893A
公开(公告)日：1999-03-09
申请号：JP22772997
申请日：1997-08-25
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： MATSUNO TAKASHI , ABE SUSUMU , OYA YOICHI , SUKEGAWA FUMIO , SAKAGUCHI YASUHIRO
IPC分类号： G06F11/30
摘要： PROBLEM TO BE SOLVED: To obtain a circuit which can easily set an arbitrary wait time by allowing a watchdog timer to perform watchdog time-out detection and wait time setting up to hardware resetting after the watchdog time-out detection. SOLUTION: A watchdog time-out value is set in a watchdog time-out value setting circuit 10 and a wait time up to hardware reset issue after watchdog time-out detection is set in a hardware reset wait value setting circuit 11 respectively. A watchdog time-out value/hardware reset wait value selecting circuit 12 selects the value from the watchdog time-out value setting circuit 10 when a watchdog time-out detection signal 101 is negated and the value from the hardware reset value setting circuit 11 when the asserted respectively and sends it out to a time-out detecting circuit 13.

2. 发明专利

JPH114242A D CHANNEL CONTENTION CONTROL METHOD FOR ISDN AND DEVICE FOR USING ISDN 失效
公开(公告)号：JPH114242A
公开(公告)日：1999-01-06
申请号：JP15648697
申请日：1997-06-13
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： ABE SUSUMU , SAKAGUCHI SEISUKE , SUKEGAWA FUMIO
IPC分类号： H04M11/00 , H04L12/02 , H04L12/40
摘要： PROBLEM TO BE SOLVED: To collect the transmission processing circuits of a B channel and a D channel into one and to increase the number of supporting lines in a device executing point/multi-bus connection with the basic interface of an ISDN network. SOLUTION: A D channel contention control circuit 103 is provided between a layer 1 control circuit 101 and a layer 2 control circuit 102. The D channel contention control circuit 103 monitors a transmission data signal, a synchronizing signal and a clock signal between the layer 1 control circuit 101 and the layer 2 control circuit 102, discriminates the time slot position of D channel data in the transmission data signal and recognizes that D channel data is in the middle of transmission. The D channel contention control circuit 103 monitors a D channel contention detection signal which the layer 1 control circuit 101 outputs. When D channel contention occurs during D channel data transmission, only D channel data in transmission data is invalidated.

3. 发明专利

JPH08149456A CAMERA SWITCHOVER SYSTEM 失效
公开(公告)号：JPH08149456A
公开(公告)日：1996-06-07
申请号：JP28167694
申请日：1994-11-16
申请人： HITACHI LTD
发明人： OYA YOICHI , SUKEGAWA FUMIO
IPC分类号： H04N7/18 , H04L12/42
摘要： PURPOSE: To obtain a camera switchover system which is effective for switching the images of the plural cameras connected with nodes and displaying the image on a monitor, in a loop LAN. CONSTITUTION: In the loop LAN which is composed of plural nodes 21 to 24 and a transmission line 1 connecting the nodes on a loop, connects each node with a monitor 6, plural camera switch controllers 31 to 39 and cameras 41 to 49 and switches the images of the cameras by the instruction from a monitor side, output node information and output camera information are provided in a transmission frame revolving around the transmission line 1. The switchings of the images of the plural cameras to be connected with the loop LAN can be realized by a simple H/W constitution, and also the confirmation of a switch operation as to whether the outputs to the loop of the images from the nodes are rightly performed or not can be realized.

4. 发明专利

JPS6464436A COMMUNICATION SYSTEM 失效
公开(公告)号：JPS6464436A
公开(公告)日：1989-03-10
申请号：JP22048387
申请日：1987-09-04
申请人： HITACHI LTD
发明人： SUKEGAWA FUMIO
摘要： PURPOSE:To improve the utilizing efficiency of a time slot and to obtain efficient activity by adding information to identify the receiving opponent of data loaded on a time slot group into the time slot. CONSTITUTION:A signal frame is formed by the time slot for synchronizing and the plural time slots for data and divided into the plural time slot groups for data. As receiving opponent identifying information to show wether the data to be loaded on the time slot group are the data from a master station to a slave station or the data from the slave station to the master station, the two act bits of an ACTM bit to show to be the data from the master station and an ACTS bit to show to be the data from the slave station are added. Thus, the utilizing efficiency of the time slot can be improved.

5. 发明专利

JPS6264150A TIME DIVISION MULTIPLEX TRANSMITTER 失效
公开(公告)号：JPS6264150A
公开(公告)日：1987-03-23
申请号：JP20326785
申请日：1985-09-17
申请人： HITACHI LTD
发明人： SUKEGAWA FUMIO
摘要： PURPOSE:To improve the utilizing efficiency of a time slot by adding the information representing an opposite transmitter received to each time slot so as to apply data exchange in one time slot per line. CONSTITUTION:A data received by an interface control circuit 31 is stored in a transmission buffer temporarily, a value of a reception control bit designation register 28 is added as a reception control bit by a reception control bit addition circuit 27, inserted in a time slot designated by a time slot designation register 25 by a time slot selection circuit 24 and sent to a loop transmission line 1 via a frame detection circuit 23 and a transmission circuit 22. On the other hand, a frame circulating through the transmission line 1 is subject to frame synchronization detection, decomposed at each time slot by the circuit 23 and a data of the time slot designated by the register 25 is selected by the circuit 24 and only when the reception control bit included in the time slot is coincident with the complement of the value in the register 28, the data is inserted to a reception buffer 29 from a reception control bit check circuit 26 and sent via the circuit 31.

6. 发明专利

JP2000278261A ISDN CONNECTION DEVICE 失效
公开(公告)号：JP2000278261A
公开(公告)日：2000-10-06
申请号：JP8539099
申请日：1999-03-29
申请人： HITACHI LTD
发明人： SUKEGAWA FUMIO , SHIRAISHI TSUTOMU , KAMENO HIDEJI
IPC分类号： H03L7/10 , H04L1/22 , H04L7/033 , H04L12/02 , H04M11/00 , H04Q11/04
摘要： PROBLEM TO BE SOLVED: To prevent disturbance in an output clock at the switching of an input clock of a PLL to generate a multiplex clock in a clock changeover control circuit of an ISDN connection device. SOLUTION: The ISDN connection device comprising a plurality of ISDN interface circuits (ISDN i/f0-n) 4-0-4-n, a channel data transmission reception section that controls transmission reception of data multiplexed on a channel, a PLL (1-2) to take synchronization of a clock and a clock changeover control circuit 1, multiplexing data of a plurality of the ISDN interface circuits (ISDN i/f0-n) 4-0-4-n by using a high speed clock synchronously with an ISDN and giving the result to the channel data transmission reception section 3 that applies transmission reception processing to the data in a lot is configured such that two frequency dividers (frequency divider A) for a system A and (frequency divider B) for a system B of a PLL are provided to the clock changeover control circuit, and a circuit selecting sequentially a clock for phase matching for an active/standby system is provided.

7. 发明专利

JPH0715457A DIGITAL COMMUNICATION SWITCHOVER SYSTEM 失效
公开(公告)号：JPH0715457A
公开(公告)日：1995-01-17
申请号：JP14744193
申请日：1993-06-18
申请人： HITACHI LTD , HITACHI COMPUTER ELECTRONIC
发明人： SUKEGAWA FUMIO , FURUSAWA TAKESHI , SUGIMOTO FUMINORI , OYA YOICHI
IPC分类号： H04N5/232 , H04L12/42
摘要： PURPOSE:To provide an effective digital communication switchover system to switch over pictures of plural cameras connecting to a node and to display the picture onto a monitor in a loop LAN. CONSTITUTION:A loop LAN which is made up of plural odes 2A-2D and a transmission line 1 connecting them as a loop and in which a monitor 3 and plural cameras 61-63 are connected to each node and the picture of the cameras is switched over by a command from the monitor is provided with output command information, picture synchronizing signal information and replay monitor information in a transmission frame circulated through the transmission line 1. Thus, the changeover of the plural cameras 61-63 is realized with simple hardware configuration and disturbance of the picture at the time of switch over is prevented and abnormal picture data are monitored.

8. 发明专利

JPH04211545A CONTROL INFORMATION TRANSMISSION SYSTEM FOR RING LAN SYSTEM 失效
公开(公告)号：JPH04211545A
公开(公告)日：1992-08-03
申请号：JP3284991
申请日：1991-02-27
申请人： HITACHI LTD
发明人： NAKAYAMA HARUYUKI , SUKEGAWA FUMIO , TAKIYASU YOSHIHIRO
IPC分类号： H04J3/08 , H04L12/43 , H04L12/437 , H04Q11/04
摘要： PURPOSE:To fixedly provide a system control information transmission area in a transmission frame and to efficiently utilize the area. CONSTITUTION:A receiving control information processing part 17 transmits the information required to be transmitted to a downstream node out of system control information received from a receiving frame resolution part 41 to a transmission control information generation part 61. The transmission control information generation part 61 creates system control information to be stored in the system control information transmission area within the transmission frame and to be transmitted to downstream by utilizing the received information and system control information generated by its node. Thus, the system control information transmission area can be efficiently shared among each node.

9. 发明专利

JPH1098490A INTERNETWORK CONNECTOR 失效
公开(公告)号：JPH1098490A
公开(公告)日：1998-04-14
申请号：JP24961696
申请日：1996-09-20
申请人： HITACHI LTD
发明人： SUKEGAWA FUMIO , OYA YOICHI , MATSUNO TAKASHI
IPC分类号： H04L1/22 , H04L12/28 , H04L12/46 , H04L12/66 , H04L29/14
摘要： PROBLEM TO BE SOLVED: To provide duplex configuration improving reliability and portability by combining singlet controllers by exchanging state information between a '0' system controller and a '1' system controller, switching the connection of a line to one device while controlling a line switching device when the other device breaks down, and continuously operating the device. SOLUTION: When one controller NP stops because of any fault, the operation is continued by switching the controller to connect the line. The fault is detected by a '0' system controller NP(0)/'1' system controller NP(1) / duplex controller DCM and the device, where the fault is detected, instructs the switching of the line through the duplex controller DCM to a line switching device LCE. The '0/1' system controller NP mutually performs a polling response and monitors the operation each other. When there is no response to polling and there is no report about the fault of the opposite side controller NP from the duplex controller DCM, '0' system switching is instructed to all the line switching devices LCE and the operation is continued closer to '0' system.

10. 发明专利

JPH05199246A NETWORK TEST SYSTEM 失效
公开(公告)号：JPH05199246A
公开(公告)日：1993-08-06
申请号：JP726692
申请日：1992-01-20
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： YAKETA TOYOKI , SUKEGAWA FUMIO , MOTOKI YOSHIKO
IPC分类号： H04L12/42
摘要： PURPOSE:To facilitate the test in the network by providing a test data generating circuit and a collation circuit used in common for testing a network transmission line, a communication opposite party interface device side and a data line in both directions. CONSTITUTION:A transient data frame state is formed between an S/P conversion circuit 101 and a transmission buffer memory 104 of an interface device 1. and between a reception buffer memory 105 and a P/S conversion circuit 108 in the case of frame format conversion. Then the test pattern is produced by the test data producing circuit 110 and selectors 102, 106, 109 are changed over by a selection signal from a test setting circuit 112 at the test, and a test data collection circuit 111 collates the test data generated by the circuit 110 with received test data. Through the constitution above, the test of a network transmission line 3, communication opposite party interface devices I2-In and synchronization system multiplex data lines 41-4n is easily conducted.

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