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1. 发明专利

JPH04132085A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH04132085A
公开(公告)日：1992-05-06
申请号：JP25003890
申请日：1990-09-21
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： OHATA KENICHI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , NANBU HIROAKI , IDEI YOJI , YAMASHITA HIROKI , SAKURAI YOSHIAKI
IPC分类号： G11C11/416
摘要： PURPOSE:To eliminate the increase of access time due to the cross talk noise of the bit line at the time of writing and to realize high integration and high- speed by providing a means supplying current only to a pair of selected bit lines. CONSTITUTION:A bit line electric potential is clamped by a pair of bipolar transistors MIB10 and MIB11 where an emitter is connected to a pair of bit lines. By allowing relatively large current to flow to a pair of selected bit lines B10 and B11, the output impedance of the bit lines B10 and B11 from bipolar transistors MIB10 and MIB11 is reduced and the cross talk noise on the bit lines B10 and B11 can be suppressed to be small. Thus, the increase of the access time due to noises at the time of writing can be prevented and the highly integrated and high-speed semiconductor memory can be formed.

2. 发明专利

JP2012165125A Calibration circuit and analog-digital converter 审中-公开
标题翻译：校准电路和模拟数字转换器
公开(公告)号：JP2012165125A
公开(公告)日：2012-08-30
申请号：JP2011022896
申请日：2011-02-04
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： FUKUDA KOJI , YAMASHITA HIROKI
IPC分类号： H03M1/10 , H03M1/36
摘要： PROBLEM TO BE SOLVED: To provide a technique for calibrating many circuits of the same configuration, with small area, low power and high accuracy.SOLUTION: A calibration circuit includes: analog voltage holding circuits 15-15for respective comparators 2-2each including a capacity capable of holding an analog control voltage value for a given time; digital memories 12-12for the respective comparators 2-2each for storing a current digital control value; one highly accurate DAC 20 for receiving the current digital control values stored in the digital memories 12-12and converting the digital control values to output analog control voltage values; and a controller 30 for setting the current digital control values stored in the digital memories 12-12of the respective comparators 2-2in the DAC 20 in order, to periodically refresh the capacities of the analog voltage holding circuits 15-15.
摘要翻译：要解决的问题：提供一种用于校准具有小面积，低功率和高精度的相同配置的许多电路的技术。
解决方案：校准电路包括：各比较器2的SB模拟电压保持电路15 SB SB =“POST”> 1 N 1 -2 N ，其中包括能够在给定时间内保持模拟控制电压值的容量; 对于各个比较器2的数字存储器12 1 -12 N 1 < 2 N ，用于存储当前数字控制值; 一个高精度DAC20，用于接收存储在数字存储器12中的当前数字控制值12 1 -12 N 控制值输出模拟控制电压值; 以及用于设置存储在各个比较器2的数字存储器12中的当前数字控制值的控制器30（SB SB =“POST”> 1 -12 N DAC 20中的 1 -2 N ，以周期性地刷新模拟电压保持电路15的容量 1 -15 N 。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2012156763A Transmission circuit 有权
标题翻译：传输电路
公开(公告)号：JP2012156763A
公开(公告)日：2012-08-16
申请号：JP2011013795
申请日：2011-01-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KURAHASHI HIROAKI , HOKARI TOMOFUMI , MUTO TAKASHI , ONO TAKEKAZU , YAMASHITA HIROKI
IPC分类号： H03K5/125 , H03K19/0175
CPC分类号： H03K19/018514
摘要： PROBLEM TO BE SOLVED: To provide a transmission circuit that can solve an imbalance in emphasis between high and low output level sides with two advantages of correction circuit elimination and element circuit occupation area reduction over existing transmission circuits.SOLUTION: In the transmission circuit, a driver circuit 17 has MOS transistors M3p, M3n for bias voltage application cascode-connected to MOS transistors M1p, M1n for differential signal input controlled by a voltage value of a transmission data signal, and controlled by a voltage value of a bias voltage to conduct a driving current, and driver circuits 16, 18 have MOS transistors M3p, M3n for bias voltage application cascode-connected to MOS transistors M1p, M1n for differential signal input controlled by a voltage value of a delayed signal of the transmission data signal and connected to load sections, and controlled by a voltage value of a bias voltage to conduct a driving current.
摘要翻译：要解决的问题：提供一种可以解决高输出电平侧和低输出电平侧之间的不平衡的发送电路，其具有校正电路消除和元件电路占用面积减少在现有传输电路上的两个优点。解决方案：在传输电路中，驱动器电路17具有MOS晶体管M3p，M3n，用于与用于通过传输数据信号的电压值控制的差分信号输入的MOS晶体管M1p，M1n共源共栅放电的偏压施加，并控制通过施加驱动电流的偏置电压的电压值，并且驱动电路16,18具有MOS晶体管M3p，M3n，用于与MOS晶体管M1p，M1n连接的偏置电压施加，用于由电压值为传输数据信号的延迟信号并连接到负载部分，并由偏置电压的电压值控制以传导驱动电流。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2011221386A Optical transmission module and optical communication apparatus using the same 有权
标题翻译：光传输模块和光通信设备
公开(公告)号：JP2011221386A
公开(公告)日：2011-11-04
申请号：JP2010092069
申请日：2010-04-13
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YUKI FUMIO , YAMASHITA HIROKI , TSUJI SHINJI , SHINODA KAZUNORI
IPC分类号： G02B6/42 , H01S5/022 , H01S5/026 , H01S5/10
CPC分类号： G02B6/43 , G02B6/4204 , G02B6/4214 , G02B6/4249 , G02B6/4257 , G02B6/428 , H01L2224/16225 , H01L2924/15311 , H01S5/0224 , H01S5/02284 , H01S5/02288 , H01S5/02292 , H01S5/024
摘要： PROBLEM TO BE SOLVED: To improve a heat radiation property of an optical transmission module.SOLUTION: An optical element 20 which an optical transmission module comprises has a principal surface (a first principal surface) 20a which is a light receiving/emitting surface and a principal surface on the opposite side of the principal surface 20a (a second surface) 20b, and is mounted on a wiring board by a flip-chip connection method through a plurality of bump electrodes formed on the principal surface 20b. A lens (an optical lens) 12 is fixed to the principal surface 20a side of the optical element 20. A heat radiation block (a heat radiation member) 16 is fixed between the optical element 20 and the lens 12, and the undersurface of the heat radiation member (a first surface) 16a abuts on the principal surface 20a of the optical element 20.
摘要翻译：要解决的问题：提高光传输模块的散热性能。解决方案：光传输模块包括的光学元件20具有作为光接收/发射表面的主表面（第一主表面）20a和在主表面20a的相对侧上的主表面（第二主表面）表面）20b，并且通过倒装芯片连接方法通过形成在主表面20b上的多个凸块电极安装在布线板上。透镜（光学透镜）12固定在光学元件20的主表面20a侧。散热块（散热构件）16固定在光学元件20和透镜12之间，并且散热构件（第一表面）16a邻接光学元件20的主表面20a。（C）2012，JPO和INPIT

5. 发明专利

JP2011166260A Output driver circuit 有权
标题翻译：输出驱动电路
公开(公告)号：JP2011166260A
公开(公告)日：2011-08-25
申请号：JP2010023970
申请日：2010-02-05
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： FUKUDA KOJI , YAMASHITA HIROKI
IPC分类号： H03K19/0175 , H03K17/687 , H03K19/0948
CPC分类号： H03K5/151 , H03K19/01721 , H04L25/0272 , H04L25/0278 , H04L25/0282 , H04L25/0286 , H04L25/03878
摘要： PROBLEM TO BE SOLVED: To provide an output driver circuit which increases communication speed, reduces power consumption or improves transmission waveform quality. SOLUTION: The output driver circuit has a voltage signal generation circuit block VSG_BK which drives positive and negative output nodes (TXP and TXN) using voltage, pulse signal generation circuits PGEN1 and PGEN2 which generate a pulse signal after transition of data input signals DIN_P and DIN_N, and current signal generation circuit blocks ISG_BKp1 and ISG_BKn1 which drive TXP and TXN using current at a pulse width period of the pulse signal. The current signal generation circuit block charges parasitic capacitances (Cp1 and Cp2) of TXP and TXN at high speed, and performs pre-emphasis according to the pulse width. VSG_BK determines a voltage level in the steady state at TXP and TXN, and terminates TXP and TXN in an impedance Z0. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供增加通信速度的输出驱动器电路，降低功耗或提高传输波形质量。
解决方案：输出驱动器电路具有电压信号产生电路块VSG_BK，其使用电压脉冲信号产生电路PGEN1和PGEN2驱动正和负输出节点（TXP和TXN），脉冲信号产生电路PGEN1和PGEN2在数据输入信号转换之后产生脉冲信号 DIN_P和DIN_N以及在脉冲信号的脉冲宽度周期使用电流驱动TXP和TXN的电流信号产生电路块ISG_BKp1和ISG_BKn1。当前信号发生电路块高速地对TXP和TXN的寄生电容（Cp1和Cp2）进行充电，并根据脉冲宽度进行预加重。 VSG_BK确定在TXP和TXN处于稳定状态的电压电平，并且在阻抗Z0中终止TXP和TXN。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2010035106A Variable delay circuit 审中-公开
标题翻译：可变延迟电路
公开(公告)号：JP2010035106A
公开(公告)日：2010-02-12
申请号：JP2008197646
申请日：2008-07-31
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMASHITA HIROKI , FUKUDA KOJI , NEMOTO AKIRA
IPC分类号： H03K5/13
摘要： PROBLEM TO BE SOLVED: To provide a variable delay circuit capable of easily expanding an adjustment range of delay time. SOLUTION: A variable delay circuit is provided with: a delay circuit block DLY_BK1 for delaying differential input signals through a plurality of stages of delay circuits DLY[1] to DLY[n]; and a duty ratio correction block DTCTL_BK1a for correcting a duty ratio through waveform addition and then outputting differential output signals. A DLY[k] ((k) is 1 to (n)) includes two CMOS inverter circuits for transmitting the differential signals, respectively, with a potential difference between a power supply voltage VDD and a common node CMN[k] as a driving voltage, an NMOS transistor MN3[k] and a capacitor C[k] for regulating and stabilizing a potential of CMN[k]. Each of the delay circuits DLY is operable with low power without incurring phase deviation between differential signals, so that multi-stage connection can be performed thereon. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供能够容易地扩展延迟时间的调整范围的可变延迟电路。解决方案：可变延迟电路具有延迟电路块DLY_BK1，用于延迟通过多级延迟电路DLY [1]至DLY [n]的差分输入信号; 以及用于通过波形相加校正占空比然后输出差分输出信号的占空比校正块DTCTL_BK1a。 DLY [k]（（k）为1至（n））包括两个CMOS反相器电路，用于分别以电源电压VDD和公共节点CMN [k]之间的电位差作为驱动发送差分信号电压，用于调节和稳定CMN [k]的电位的NMOS晶体管MN3 [k]和电容器C [k]。每个延迟电路DLY可以以低功率工作，而不会引起差分信号之间的相位偏移，从而可以对其进行多级连接。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2008167094A Level conversion circuit 有权
标题翻译：电平转换电路
公开(公告)号：JP2008167094A
公开(公告)日：2008-07-17
申请号：JP2006353595
申请日：2006-12-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMASHITA HIROKI , YUKI FUMIO , NEMOTO AKIRA , KANAI HISAAKI , YAMAMOTO KEIICHI
IPC分类号： H03K19/0185 , H03K19/0948
CPC分类号： H03K19/094 , H03K19/018521
摘要： PROBLEM TO BE SOLVED: To provide a technique achieving a low power and a high-speed operation and being capable of inhibiting the fluctuation of input-output characteristics by a power-supply voltage, a temperature change and the dispersion or the like of device characteristics in a level conversion circuit.
SOLUTION: The level conversion circuit has a source follower circuit 603 with a transistor NM1 inputting an AC signal at a CML level and the transistor NM2 inputting a control voltage Vc and a control-voltage generating circuit 602 generating the control voltage Vc inputting the transistor NM2. The control-voltage generating circuit 602 has a replica source follower circuit 604 as a replica for the source follower circuit 603 with the transistor NM3 inputting a central voltage at the CML level and the transistor NM4 inputting the control voltage Vc. The control-voltage generating circuit 602 further has a comparator 605 controlling the control voltage Vc so that the output voltage of the replica source follower circuit 604 and a CMOS-circuit threshold voltage Vcmosth are equalized.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种实现低功率和高速操作的技术，并且能够通过电源电压，温度变化和分散等来抑制输入 - 输出特性的波动的电平转换电路中的器件特性。解决方案：电平转换电路具有源极跟随器电路603，其具有以CML电平输入AC信号的晶体管NM1和输入控制电压Vc的晶体管NM2和产生控制电压Vc输入的控制电压产生电路602 晶体管NM2。控制电压产生电路602具有作为源极跟随器电路603的复制品的复制源极跟随器电路604，其中晶体管NM3输入CML电平的中心电压和输入控制电压Vc的晶体管NM4。控制电压产生电路602还具有控制控制电压Vc的比较器605，使得复制源极跟随器电路604的输出电压和CMOS电路阈值电压Vcmosth相等。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2008061132A Transceiver, transmitter, and receiver 有权
标题翻译：收发器，发射器和接收器
公开(公告)号：JP2008061132A
公开(公告)日：2008-03-13
申请号：JP2006238161
申请日：2006-09-01
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TOYODA HIDEHIRO , SAITO TATSUYA , YAMASHITA HIROKI , NAKAJO TOKUO
IPC分类号： H04L7/033 , H04L7/00
CPC分类号： H04L7/0337
摘要： PROBLEM TO BE SOLVED: To provide transmission/reception techniques, with which throughput of a data channel can be improved by reducing a load applied to a data signal line, while maintaining the communication quality. SOLUTION: A transceiver includes, on the transmission side, an encoder circuit 11 which transmits a bit data stream, resulting from encoding link information, to a clock signal line. On the reception side, the transceiver includes a clock data reproducing circuit 17 which extracts the clock component from a signal received from the clock signal line, a decoder circuit 19 which reproduces the link information by decoding the extracted signal, and a bit deskew circuit 21 which adjusts the skew smaller than 1 bit, based on the clock component. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供发送/接收技术，通过减少施加到数据信号线的负载来提高数据信道的吞吐量，同时保持通信质量。解决方案：收发器在发送侧包括编码器电路11，其将由编码链接信息产生的比特数据流发送到时钟信号线。在接收侧，收发器包括时钟数据再现电路17，其从从时钟信号线接收到的信号中提取时钟分量;解码器电路19，其通过解码提取的信号再现链接信息;以及位歪斜电路21 其基于时钟分量来调整小于1位的偏移。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2004180188A Data reproducing method and digital control type clock data recovery circuit 有权
公开(公告)号：JP2004180188A
公开(公告)日：2004-06-24
申请号：JP2002346767
申请日：2002-11-29
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YUKI FUMIO , YAMASHITA HIROKI , SONEHARA MICHIHITO
IPC分类号： H03L7/081 , H03L7/091 , H04J3/06 , H04L7/02 , H04L7/033
CPC分类号： H04L7/0331 , H03L7/0814 , H03L7/091 , H03L2207/50 , H04L7/0337
摘要： PROBLEM TO BE SOLVED: To expand a jitter tolerance (1), to expand a range where data can be acquired when a wander occurs (2), to improve the followability of a reproduction clock to the wander (3) and to attain the low power consumption of a circuit (4). SOLUTION: Data 101 are compared with an edge position of a data obtaining clock (reproduction clock) 102. If the interval resulting from the comparison falls below a reference value, a clock edge is made far from a data edge. In addition, a synthesis circuit and the simultaneous on-control of two control signals of an 8-1 selector generate a clock of an N phase obtained by dividing one cycle into N parts from a reference clock 109 and select a data obtaining clock in the clock of the N phase. COPYRIGHT: (C)2004,JPO

10. 发明专利

JPH11191609A LOW-NOISE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH11191609A
公开(公告)日：1999-07-13
申请号：JP35926097
申请日：1997-12-26
申请人： HITACHI LTD
发明人： TANAKA KATSUYA , YAGYU MASAYOSHI , SAITO TATSUYA , KAMIMURA TETSUYA , IWANAGA TOMOHISA , YAMASHITA HIROKI , KATO TAKESHI
IPC分类号： H01L27/04 , H01L21/822 , H03K19/003
摘要： PROBLEM TO BE SOLVED: To suppress power supply noise by supplying an integrated circuit, at a predetermined time with a quantity of charge determined in accordance with the quantity of power supply noise. SOLUTION: A noise reduction circuit 101 has a plurality of charge supply circuits 105-108 for supplying charges to VDD. When operation of an integrated circuit 102 due to deficiency in the quantity of a charge Q of VDD and a power supply noise of -ΔVDD is generated, a charge quantity determining circuit 104 determines the combination of charge supply circuits 105-108 sufficient for supplying the VDD with the quantity of the charge Q and delivers a control signal to the noise reduction circuit 101. A phase adjustment circuit 103 synchronizes the time, to the time when the noise reduction circuit 101 supplies the quantity of charge Q to the VDD with the generating time of noise -ΔVDD. A noise +ΔVDD is generated by the charge Q which is outputted from the noise reduction circuit, and cancels the power supply noise of -ΔVDD.

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