专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2001077646A LIGHT-RECEIVING DEVICE 失效
公开(公告)号：JP2001077646A
公开(公告)日：2001-03-23
申请号：JP24843799
申请日：1999-09-02
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： MASUDA TORU , OHATA KENICHI , WASHIO KATSUYOSHI
IPC分类号： H03F3/08 , H03G3/30 , H04B10/07 , H04B10/40 , H04B10/50 , H04B10/60 , H04B10/69 , H04B10/80 , H04B10/28
摘要： PROBLEM TO BE SOLVED: To reduce a source voltage by composing an automatic gain control amplifying circuit of a variable transconductance circuit, which varies with the voltage applied to a transconductance adjustment terminal and an active load circuit, equipped with a bias circuit which shunts respective output currents of the variable transconductance circuit. SOLUTION: This variable transconductance circuit 51 can be composed of one stage of a differential pair by inserting potential difference generating circuits 31a and 31b between the bases of transistors Q1 and Q2, and Q3 and Q4 respectively. The active load circuit 52 with the bias circuit has its voltage drop reduced by making the output current of the variable transconductance circuit 51 flow directly to a constant-voltage terminal V12 by the bias circuit, composed of resistances R15 and R16 inserted between the bases of transistors Q11 and Q12 and the constant-voltage terminal V12 for the highest-order voltage of the optical reception device.

2. 发明专利

JPH11339479A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH11339479A
公开(公告)日：1999-12-10
申请号：JP14067498
申请日：1998-05-22
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD , HITACHI DEVICE ENG
发明人： KANETANI KAZUO , NANBU HIROAKI , YAMAZAKI SU , OHATA KENICHI , ARAKAWA FUMIHIKO , KUSUNOKI TAKESHI , HIGETA KEIICHI , NISHIYAMA MASAHIKO , YAMAGUCHI KUNIHIKO
IPC分类号： G11C11/413 , G11C11/414
摘要： PROBLEM TO BE SOLVED: To limit the level of a control signal for a switch discharging a signal line selectively below the withstanding voltage of the switch while guaranteeing that no discharge current flow through the signal line during nondischarging period thereof. SOLUTION: The semiconductor integrated circuit comprises a first bipolar transistor QDC having emitter connected with a current source IDC and collector connected with a load W, a switch MN having one end connected with the load and the other end connected with the base of the transistor, and a logic circuit D for controlling the current flowing through a first bipolar transistor QDC into the load W by turning the switch MN on/off. The semiconductor integrated circuit further comprises a level shift circuit LS receiving the output from the logic circuit D and the output of the level shift circuit LS is connected with the control terminal of the switch MN.

3. 发明专利

JPH11328970A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH11328970A
公开(公告)日：1999-11-30
申请号：JP13645398
申请日：1998-05-19
申请人： HITACHI LTD , HITACHI DEVICE ENG , HITACHI ULSI SYS CO LTD
发明人： NANBU HIROAKI , KANETANI KAZUO , YAMAZAKI SU , OHATA KENICHI , ARAKAWA FUMIHIKO , KUSUNOKI TAKESHI , HIGETA KEIICHI , NISHIYAMA MASAHIKO , YAMAGUCHI KUNIHIKO , SAEKI TETSUYA
IPC分类号： G11C11/41 , G11C11/413
摘要： PROBLEM TO BE SOLVED: To achieve reduction in power consumption and a cycle time of a semiconductor memory incorporating a writing pulse generation circuit. SOLUTION: A frequency-divided signal DDI dividing a clock pulse is compared with an output signal of a pseudo-memory cell in a comparison circuit CMP to make a dummy writing signal to '1', and inverse writing is performed in a pseudo-memory cell by the frequency-divided signal concurrently with this, and the dummy writing signal is returned to '0' by the comparison circuit to which the reversing signal and the frequency-divided signal of the pseudo- memory cell are inputted. Instead of a signal changed over twice a cycle as a signal for controlling the reverse writing in the pseudo-memory cell, a frequency-divided signal changed over only once a cycle is used. And, an operation delay time of the comparison circuit is not included in the pulse width of the dummy writing signal. As a result, it is possible to reduce the electric power consumed by the electrical charge and discharge of the dummy bit line to a half of a conventional one, and also shorten the cycle time.

4. 发明专利

JPH07282579A DRIVING CIRCUIT 失效
公开(公告)号：JPH07282579A
公开(公告)日：1995-10-27
申请号：JP7306094
申请日：1994-04-12
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： OHATA KENICHI , NANBU HIROAKI , KANETANI KAZUO , IDEI YOJI , MASUDA TORU , KUSUNOKI TAKESHI
IPC分类号： G11C11/407 , H03K19/0175
摘要： PURPOSE:To obtain a sufficient wiring delay reducing effect by connecting drains of transistors of PMOSes and NMOSes with a common output terminal and controlling gate potentials in accordance with an input signal while connecting sources respectively with different power sources. CONSTITUTION:When a signal IN changes now from a low potential to a high potential, a GP1, a GP2 and a GN2 become the high potential and a GN1 becomes the low potential. Consequently, a transistor MN2 conducts and then an output A is lowered to a VSHAfter a time DELTAt, the GN2 changes to the low potential and simultaneously the GN1 changes to the high potential. Consequently, an MN1 conducts in stead of the resistor MN2 and then the A is raised from the VSH to a VSS. On the other hand, when the signal IN changes from the high potential to the low potential, a transistor MP2 conducts for a first DELTAt and then the A is raised to a VCH. Thereafter, a transistor MP1 conducts in stead of the transistor MP2 and then the A is lowered from the VCH to a VCC. Thus, a signal whose amplitude is made large temporarily at the time of a changeover can be obtained.

5. 发明专利

JPH07249981A SEMICONDUCTOR CIRCUIT 失效
公开(公告)号：JPH07249981A
公开(公告)日：1995-09-26
申请号：JP3941694
申请日：1994-03-10
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , KANETANI KAZUO , IDEI YOJI , MASUDA TORU , OHATA KENICHI , KUSUNOKI TAKESHI
IPC分类号： H01L21/822 , H01L27/04 , H03K19/018
摘要： PURPOSE:To prevent the increase of the consumption power by allowing the through current to a CMOS circuit and to prevent the deterioration of the speed of an ECL circuit. CONSTITUTION:The level of a signal OL outputted by an ECL circuit (OLI, OL2,... OEL or the like) is controlled by the power supply voltage VSS of the CMOS circuit driven by the ECL circuit. The level VBB of the input reference potential of the ECL circuit is controlled by the power supply voltage VBB of the CMOS circuit which drives the ECL circuit. Thus, the relative electric potential relation between the L level VLE of the signal to be outputted from the ECL circuit and the power supply voltage VSS of the CMOS circuit can be kept constant so that the NMOS in the CMOS circuit is turned on and the through current passes in the CMOS circuit, resulting in preventing the increase of the consumption power. The relative electric potential relation between the input reference potential VBB of the ECL circuit and the power supply voltage VSS of the CMOS circuit can be almost constant so that the deterioration of the speed of the ECL circuit can be prevented.

6. 发明专利

JPH07231249A DRIVER CIRCUIT 失效
公开(公告)号：JPH07231249A
公开(公告)日：1995-08-29
申请号：JP2087394
申请日：1994-02-18
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KANETANI KAZUO , NANBU HIROAKI , IDEI YOJI , MASUDA TORU , OHATA KENICHI , KUSUNOKI TAKESHI
IPC分类号： H03K17/567 , H03K17/66
摘要： PURPOSE:To reduce power consumption of the driver circuit by connecting a drain of an input transistor(TR) to a collector and a babe of a 1st TR, connecting a collector of a 2nd TR to a base of an output TR and connecting an emitter of the output TR to a collector of a 3rd TR. CONSTITUTION:When an input IN1 is set to an L level, a source-gate voltage of a TR MP1 is higher than a threshold voltage, the TR MP1 is conductive and a current is supplied to an NPN TRQ1. Thus, a current is generated in 2nd and 3rd NPN TRs Q2, Q3 being a current mirror current source. That is, a drive current IC is generated in the TRQ2 and an emitter follower current IEF is generated in the TRQ3. The current IC flows to a resistor R1 to set a base potential of an output NPN TR Q4 to be low and an output terminal being an emitter of the TRQ4 is discharged at a high speed by the current IEF to be set to be low. The currents IC, IEF of the driver circuit are generated when the input is at an L level and not generated when the input is at an H level. Thus, power consumption is reduced.

7. 发明专利

JPH0697747A EMITTER FOLLOWER CIRCUIT 失效
公开(公告)号：JPH0697747A
公开(公告)日：1994-04-08
申请号：JP24295992
申请日：1992-09-11
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KANETANI KAZUO , HONMA NORIYUKI , NANBU HIROAKI , IDEI YOJI , OHATA KENICHI , KUSUNOKI TAKESHI
IPC分类号： H03F1/02 , H03F3/50 , H03K19/086
摘要： PURPOSE:To reduce the power consumption of the emitter follower circuit. CONSTITUTION:A drain of a MOS transistor MP of a (p) channel, a base of a pull-down transistor Q2, and one end of a discharge circuit CSW are connected, and on the other hand, a source of the pMOS MP and a collector of the pull-down transistor Q2 are connected to an emitter of an emitter follower transistor Q1. In such a state, a base of the emitter follower transistor Q1 and a gate of the pMOS MP are driven by a signal of the same phase. In such a way, at a transient time when an output OUT is switched from H to L, a large current flows to the pull-down transistor Q2, and at a transient time when its output is switched from L to H, a large current flows to the emitter follower transistor Q1. However, at a steady time of H and L, only a small current flows in both of them. Therefore, the low power consumption is attained.

8. 发明专利

JPH04281290A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH04281290A
公开(公告)日：1992-10-06
申请号：JP4352891
申请日：1991-03-08
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , IDEI YOJI , OHATA KENICHI , SAKURAI YOSHIAKI
IPC分类号： G11C11/415 , G11C11/407 , H03K19/086
摘要： PURPOSE:To increase the speed of accessing or cycling time by driving a ward line or a data line selecting signal on an ECL circuit. CONSTITUTION:A ward line driver DR of this memory is constituted of a bipolar ECL circuit. Thus, a level conversion circuit for converting the signal of an ECL level into the signal of a BiCMOS level need not be provided between a address buffer constituted of the bipolar ECL circuit and the driver DR and the delaying of an accessing time is prevented as much as delaying time at the level conversion circuit. A data line selecting signal generating circuit is constituted in the same way, as well. Also, a field-effect transistor is preferably used to drive a data line D or to detect a data line signal.

9. 发明专利

JPH04153992A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH04153992A
公开(公告)日：1992-05-27
申请号：JP27623490
申请日：1990-10-17
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , IDEI YOJI , OHATA KENICHI , SAKURAI YOSHIAKI
IPC分类号： G11C11/41 , G11C11/412
摘要： PURPOSE:To make two normally required bit lines one line with-out differing the characteristics of the two inverter circuits constituting a flip-flop by containing N-type conductive field effect transistor and P-type conductive field effect transistors in a memory cell. CONSTITUTION:A memory cell contains an N-type conductive field transistor MNTL whose drain is connected to a cell node within a memory cell, and gate is connected to a + word line WU, and a source is connected to a bit line BL. Further, the semiconductor memory is constructed to contain a P-type conductive effect transistor MPTL connecting a drain to the cell node within the memory cell, connecting a gate to a - word line WL, connecting a source to the beat line BL. Thus the two normally required lines can become one line without differing the characteristics of the two inverter circuits consisting of the flip-flop.

10. 发明专利

JPH0423509A FLIP-FLOP CIRCUIT 失效
公开(公告)号：JPH0423509A
公开(公告)日：1992-01-27
申请号：JP12673890
申请日：1990-05-18
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： OHATA KENICHI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , NANBU HIROAKI , IDEI YOJI , SAKURAI YOSHIAKI
IPC分类号： H03K3/286
摘要： PURPOSE:To operate the flip-flop circuit by a low power supply voltage and to prevent an output data signal from generating noise by constituting this flip-flop circuit without using any series gate. CONSTITUTION:The flip-flop circuit is composed of a data holding circuit and a control circuit. This data holding circuit is composed of a pair of transistors Q5 and Q7 whose base and collector are connected to each other, and load resistors R4-R6 connected to the respective collectors, and this control circuit is composed of transistors Q3, Q4, Q8 and Q9 connected so as to constitute a current switching circuit together with the transistors Q5 and Q7. Since the flip-flop circuit is constituted without using any series gate and a differential signal is not used as a clock signal, any phase difference is not generated in the clock signal. Thus, the flip-flop circuit can be obtained to be operatable by the low power supply voltage without generating noise in the output data signal.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式