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1. 发明专利

JPH10247684A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH10247684A
公开(公告)日：1998-09-14
申请号：JP4873997
申请日：1997-03-04
申请人： HITACHI LTD
发明人： OGASAWARA MAKOTO
IPC分类号： H01L21/76 , H01L27/08 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To stabilize a MISFET in characteristics by a method wherein a gate oxide film and a conductor film are formed on a semiconductor substrate, a silicon nitride film is formed on a part of the semiconductor substrate other than a groove forming part, and a part of the substrate other than the part masked with the silicon nitride film is anisotropically etched for the formation of a groove, and the surface of the substrate is polished. SOLUTION: A first conductive polycrystalline silicon film 3 is formed on a first insulating silicon dioxide film 2, the first conductive film 3 and the silicon dioxide film 2 are removed by anisotropic etching using a silicon nitride film 4 left on the conductor film as a mask, and a groove is cut in the silicon substrate for isolating elements from each other. Oxide such as silicon dioxide is filled in the groove, and the surface of the substrate is flattend by polishing, and ions are implanted into the substrate through the polysilicon film and the silicon dioxide film. Then, conductive material is deposited as a second conductive film to serve as a wiring layer. It is no region where a MISFET is hard to form.

2. 发明专利

JPH09246556A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH09246556A
公开(公告)日：1997-09-19
申请号：JP4714096
申请日：1996-03-05
申请人： HITACHI LTD
发明人： YANAGISAWA YASUNOBU , OGASAWARA MAKOTO
IPC分类号： H01L27/12 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To restrain warp and degradation which are caused by a stress remaining in an insulating layer when the insulating layer is formed by a method wherein a stress relaxation part which relaxes the stress remaining in the insulating layer is formed in the insulating layer. SOLUTION: A semiconductor substrate 2 which constitutes an SOI substrate 1 is composed of a P type silicon single crystal, and a semiconductor layer 4 is formed on it via an insulating layer. Three insulating layers 3a to 3c are laminated sequentially from the lower part. The substrate 2 ensures the strength of the substrate, and the upper and lower insulating layers 3a to 3c ensure the bonding force of the substrate 2 to the semiconductor layer 4. The intermediate insulating layer (as a stress relaxation part) 3b is a member which relaxes a stress remaining in the insulating layers 3a, 3c, and it contains a stress in a direction opposite to the residual stress in the insulating layers 3a, 3c. By this structure, the stress in the insulating layers 3a, 3c is offset by the stress in the insulating layer 3b, it is possible to restrain the warp of the SOI substrate 1 and the quality degradation of the semiconductor layer 4.

3. 发明专利

JPH0992793A DATA PROCESSING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND THE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0992793A
公开(公告)日：1997-04-04
申请号：JP24277495
申请日：1995-09-21
申请人： HITACHI LTD
发明人： OGASAWARA MAKOTO
IPC分类号： G11C11/409 , G11C11/401 , G11C11/403 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To make it possible to increase the information holding time in the memory cell of a semiconductor integrated circuit device having a DRAM by setting a precharge voltage to be applied to a data line except at a power source voltage and to the voltage value except the half of the power source voltage. SOLUTION: When a precharge voltage is represented by VP, the precharge voltage VP can be set to 0

4. 发明专利

JPH0917965A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND ITS MANUFACTURE 失效
公开(公告)号：JPH0917965A
公开(公告)日：1997-01-17
申请号：JP16733895
申请日：1995-07-03
申请人： HITACHI LTD
发明人： OGASAWARA MAKOTO , SATO KAZUE , ASANO ISAMU , ASAKURA HISAO
IPC分类号： H01L21/8247 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To materialize a RAM high in integration degree which has a nonvolatile memory function. SOLUTION: A memory cell MC is composed of a flip flop circuit consisting of MISFETs Qd1 and Qd2 for driving and MISFETs Qp1 and Qp2 , MISFETs Qt1 and Qt2 for transfer, and ferroelectric capacitors Qf1 and Qf2 connected, respectively, to the storage nodes N1 and N2 of the flip flop circuit. When the power of the memory cell is cut, the direction of polarization of ferroelectric capacitors Qf1 and Qf2 is set by controlling the power voltage VL and plate voltage Vp each, based on the information accumulated each in the storage nodes N1 and N2 , and the information accumulated in the storage nodes N1 and N2 is read out to the ferroelectric capacitors Cf1 and Cf2 and is kept.

5. 发明专利

JPH07321199A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH07321199A
公开(公告)日：1995-12-08
申请号：JP11480694
申请日：1994-05-27
申请人： HITACHI LTD
发明人： NEZU HIROKI , OGASAWARA MAKOTO , TAMARU TAKESHI
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522
摘要： PURPOSE:To form a flat layer insulation film by forming a lower layer insulation film by a plasma CVD method or a thermal CVD method and by forming an upper layer insulation film while carrying out a CVD method and sputter etching simultaneously. CONSTITUTION:A metallic film which becomes a first wiring layer 11 is deposited first and processed. A lower layer insulation film 12 of a layer insulation film is deposited on the first wiring layer 11 by a plasma CVD method or a thermal CVD method. Successively, a bias or a self-bias is applied to a substrate 1 and an upper layer insulation film 13 of a layer insulation film is formed while carrying out a CVD method and sputter etching simultaneously wherein ECR, helicon or helical is used as plasma source. After a through-hole 14 for connecting the first wiring layer 11 and a second wiring layer 15 formed later is formed by etching a layer insulating film, metal which becomes the second wiring layer 15 is deposited and processed. Thereby, stress migration resistance and electromigration resistance of a wiring can be improved.

6. 发明专利

JPS60253263A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60253263A
公开(公告)日：1985-12-13
申请号：JP10830384
申请日：1984-05-30
申请人： HITACHI LTD
发明人： OGASAWARA MAKOTO , SHIMIZU SHINJI
IPC分类号： H01L27/10 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
摘要： PURPOSE:To facilitate the design and manufacture of a groove type element, and to equalize and stabilize element characteristics by forming the orientation flat surface a semiconductor wafer in a 100 face while the in-groove side surface of the groove type element shaped to the main surface of the wafer is constituted in either of a form parallel with or vertical to the orientation flat surface. CONSTITUTION:The main surface 1a of a wafer 1 is formed in a 100 crystal face while the surface of an orientation flat 2 shaped by notching one part of the circumference of the main surface 1a is also formed in a 100 crystal face vertical to the main surface. A large number of silicon chips are shaped, and divided into each chip through dicing. A groove 13 in a square-shaped plane is shaped to one part of an active region 12 demarcated by a field insulating film 11 in the proper depth in the main surface of a silicon substrate 10. The groove 13 is constituted so that an inner side surface 15 is made parallel with or perpendicular to the orientation flat 2. Since an inner base 14 thereof is also formed flatly, it runs parallel with the main surface 1a.

7. 发明专利

JP2001244442A SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JP2001244442A
公开(公告)日：2001-09-07
申请号：JP2001008413
申请日：2001-01-17
申请人： HITACHI LTD
发明人： MIURA HIDEO , OGASAWARA MAKOTO , MASUDA HIROO , MURATA JUN , OKAMOTO NORIAKI
IPC分类号： H01L21/316 , H01L21/76 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a device structure, together with a manufacturing method, for defining an element forming region and its dimensions capable of preventing dislocation generated when an element separation region is formed on a silicon substrate in a thermal oxidation method in a semiconductor device having the element separation region. SOLUTION: In a step for forming an element separation region on a semiconductor substrate 1 by using a thermal oxidation film 2, a width (L) of a nitride silicon film for protecting the element forming region and the width (S) of an element separation region surrounding the element forming region are defined according to the depth of a shallow groove formed on a surface of the silicon substrate, when a nitride silicon film is patterned before thermal oxidation.

8. 发明专利

JPH1197648A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH1197648A
公开(公告)日：1999-04-09
申请号：JP25910597
申请日：1997-09-24
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , OKURA OSAMU , SUGIMOTO ARITOSHI , TADAKI YOSHITAKA , OGASAWARA MAKOTO , HORIGUCHI SHINJI , HASEGAWA NORIO , FUKADA SHINICHI
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a technique for realizing a long refresh time of a relief cell of a DRAM, without increasing a chip area greatly and without complicating a process. SOLUTION: The depth of a field-relaxing layer 8r of a relief cell is formed deeper than that of a field-relaxing layer 8 of an ordinary cell, by making the width of a field oxide film 3 in a region, wherein a relief cell is formed larger than the field oxide film 3 in a region where an normal memory cell is formed. Junction electric field is reduced by enlarging a depletion layer of a source and a drain (n-type semiconductor region 7) of a relief cell.

9. 发明专利

JPH0964210A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE METHOD THEREOF 失效
公开(公告)号：JPH0964210A
公开(公告)日：1997-03-07
申请号：JP22125495
申请日：1995-08-30
申请人： HITACHI LTD
发明人： YANAGISAWA YASUNOBU , OGASAWARA MAKOTO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device and having a high-reliability nonvolatile memory and manufacturing method whereby it can be easily produced. SOLUTION: A conductive layer 4 made of a material having a work function smaller than that of Si is formed under a conductive layer 5 to be floating gate electrodes of a nonvolatile memory. A conductive layer 11 made of a material having a work function smaller than that of Si is formed on the surface of an n-type semiconductor region 10 to be sources and drains of the nonvolatile memory.

10. 发明专利

JPH08241968A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH08241968A
公开(公告)日：1996-09-17
申请号：JP6404596
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/08 , H01L27/108 , H01L29/78
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which enhances the junction breakdown strength of a substrate to an element and which reduces a leakage current amount at the junction part of the substrate to the element by a method wherein an active region is not arranged in the boundary region between a first channel stopper region and a second channel stopper region. CONSTITUTION: In a DRAM, a memory cell and an n-channel MISFET in a peripheral circuit are arranged respectively on main faces inside respective different active regions in a p-type well region which is prescribed by a p-type channel stopper region formed on the main face of an inactive region in the p-type well region. Here, a p-type channel stopper region 25A which surrounds the circumference of the memory cell and an n-channel stopper region 24 in the peripheral circuit are constituted independently in separate manufacturing processes. Then, an active region Act such as the memory cell, the n-channel MISFET or the like in the peripheral circuit are not arranged in the boundary region between the p-type channel stopper region 25A and the n-type channel region 24.

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