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1. 发明专利

JPH10149682A SEMICONDUCTOR DEVICE AND COMPUTER SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH10149682A
公开(公告)日：1998-06-02
申请号：JP25164497
申请日：1997-09-17
申请人： HITACHI LTD
发明人： NAMETAKE MASATAKE , AKIOKA TAKASHI , MITSUMOTO KINYA , NAGANO TAKAHIRO , MAEJIMA HIDEO
IPC分类号： G11C11/413 , G11C11/407 , G11C11/408 , G11C11/417
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a computer system capable of fetching an external signal and being stably operated independently of the duty ratio of a clock signal. SOLUTION: This system is provided with a means for fetching an external signal ADD to an address latch 22 by a level latch, and controlling the level latch so as to be a through state at the timing when the external signal is established, controlling the level latch to a latch state in the establishing period of the external signal and moreover controlling the timing when the latch is changed over to the through state to the desired timing by the pulse generating circuit 30 inside a chip. In this constitution, since the fetching of the external signal ADD is determined from a set up timing, the system can be made high in operation speed. Moreover, the system is stably operated independently of the pulse width of an external clock CLK since the latch period is controlled by the pulse generating circuit inside the chip.

2. 发明专利

JPH07334990A SENSE CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH07334990A
公开(公告)日：1995-12-22
申请号：JP12252094
申请日：1994-06-03
申请人： HITACHI LTD
发明人： NAMETAKE MASATAKE , MITSUMOTO KINYA , AKIOKA TAKASHI , IWAMURA MASAHIRO , AKIYAMA NOBORU
IPC分类号： G11C11/416 , G11C11/409 , H03K5/003
摘要： PURPOSE:To realize a sense circuit capable of speeding up the access time and lowering the power source voltage. CONSTITUTION:At the time of taking a wired OR of outputs of plural pre-sense amplifiers 11, a common lines taking the wired OR is divided into common lines 12, 15, 20 of plural stages and respective stage-intervals are connected by emitter-followers 14, 19 and a shift-up circuit 17 is inserted at least in one stage-interval of these common lines 12, 15, 20. The shift-up circuit 17 is constituted by connecting the N side of PN junctions (D11, D12) with common lines of the prestage and by connecting the P side of them with the common lines of the poststage. Since the signal level of the common lines 15 is raised by a voltage equivalent to forward voltage drop (VD) of PN junctions and can be raised while maintaining the mutual amplitude relation of the signal with plural common line, read-out data of the memory cell whose address is selected, are selected and outputted by taking the wired OR as it is.

3. 发明专利

JPH07296597A LOGIC GATE CIRCUIT 失效
公开(公告)号：JPH07296597A
公开(公告)日：1995-11-10
申请号：JP8990294
申请日：1994-04-27
申请人： HITACHI LTD
发明人： NAMETAKE MASATAKE , IWAMURA MASAHIRO , MITSUMOTO KINYA
IPC分类号： G01R31/28 , G11C29/00 , G11C29/34 , H01L21/66 , H03K19/086
摘要： PURPOSE:To provide a parallel test circuit for a memory cell capable of performing parallel test of normal memory cells even by a low source voltage. CONSTITUTION:This circuit is provided with plural pre-sense amplifiers PSA 19, a common data bus line 15 connected commonly to the PSA 19, an MSA 17 connected to the bus line 15 and a test circuit 16. In the parallel test circuit for the memory cell, the test circuit 16 is provided with a level shift circuit 1 consisting of a multi-emitter transistor 3 of diode connection and a pull-up current source 4 and a level comparison circuit 2 provided with differential connection transistors 6, 7. The level shift circuit 1 whose two inputs are connected to the bus line 15, and the level comparison circuit 2 level compares the output of the level shift circuit 1 with a reference voltage Vref1 by the transistor 6, 7, and an AND (NAND) logical output of a logic signal supplied to the bus line 15 is led out from the collectors of the transistors 6, 7.

4. 发明专利

JPH07211075A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH07211075A
公开(公告)日：1995-08-11
申请号：JP580394
申请日：1994-01-24
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： AKIYAMA NOBORU , NAMETAKE MASATAKE , IWAMURA MASAHIRO , MITSUMOTO KINYA , OKUTSU MITSUHIKO
IPC分类号： G11C11/41
摘要： PURPOSE:To suppress an integration area and the increase of a power consumption and facilitate high speed transmission by a method wherein the lengths of wiring from address edge detecting circuits to distribution circuits through an integrated pulse generating circuit are reduced. CONSTITUTION:An integrated pulse generating circuit 7 and a first distribution circuit 8 are provided on the middle part of a semiconductor chip 15. Two address edge detecting circuits 6 are provided near the circuit 7 taking corresponding input address buffers 4 into account. Four second distribution circuit 9 are provided near the circuit 8 and corresponding memory blocks 1. Eight third distribution circuits 10 are provided near the corresponding circuits 9 and corresponding memory mats 2. With this constitution, the length of a first bus line BL1 can be smaller than the sum of the length of a second bus line BL2 and the length of a third bus line BL3. Therefore, the capacity values of the output loads of the circuits 6 and 7 can be reduced and the speed of charge/discharge caused by the transition of the ATD pulses which are the outputs of the circuits 6 and the ATD integrated pulse which is the output of the circuit 7 can be increased and the circuit constants of the circuit 6 can be reduced and the area can be reduced.

5. 发明专利

JPH01164064A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01164064A
公开(公告)日：1989-06-28
申请号：JP32137687
申请日：1987-12-21
申请人： HITACHI LTD
发明人： KOBAYASHI YUTAKA , TANBA AKIHIRO , HORI RYOICHI , ASAYAMA MASAICHIRO , NAMETAKE MASATAKE , MIYAZAWA HIROYUKI , YANAGISAWA KAZUMASA , KITSUKAWA GORO
IPC分类号： H01L27/10 , H01L21/8242 , H01L21/8249 , H01L27/06 , H01L27/108 , H01L29/94
摘要： PURPOSE:To reduce parasitic capacitance of a bipolar and to realize a high- speed operation by a method wherein the inside of a groove for isolation use is kept in a floating state from a surrounding semiconductor region by using an insulating film, an insulating layer and a conductive layer are formed alternately inside a groove for capacitance formation use of a memory cell and one conductive layer which is formed capacitance between faced conductive layers is connected to a fixed potential. CONSTITUTION:A P region 33 formed by ion implantation and an N region 62 formed by diffusion are formed at the bottom of a groove 32 for capacitance formation use of a memory cell; N polycrystalline Si 34 is separated from a P-substrate 10 by using a P-N junction so that its potential (anode potential) can be selected arbitrarily. In a device isolation groove 12, polycrystalline Si 15 is kept in a floating state by using insulating films 16; this prevents parasitic capacitance from being generated between collector regions 63 of a bipolar.

6. 发明专利

JPS62268144A MULTILAYER INTERCONNECTION STRUCTURE 失效
公开(公告)号：JPS62268144A
公开(公告)日：1987-11-20
申请号：JP11058286
申请日：1986-05-16
申请人： HITACHI LTD
发明人： MISAWA YUTAKA , NAMETAKE MASATAKE , KAWAMATA SHIGERU
IPC分类号： H01L21/768 , H01L21/31 , H01L21/3205 , H01L23/522
摘要： PURPOSE:To improve the degree of integration by operating an insulating layer consisting of either an organic film or the laminate film of the organic film and an inorganic film in order to ensure flatness in the surface, to which a wiring layer must be formed, and working an insulating layer composed of the inorganic film in order to secure stress resistance and damp-proofing. CONSTITUTION:Both insulating layers consisting of only an organic material or the organic material and an inorganic material and only the inorganic material are employed as insulating layers partitioning three layers or more of wiring layers on a substrate surface. Organic films made up of polyimide resin are used as the insulating films 30, 70 in a first layer and a third layer, thus sufficiently ensuring flatness in the surfaces, to which each wiring layer must be shaped, though the wiring layers are formed over three layers or more. A multilayer interconnection structure resists stress from the outside because an inorganic film is employed as the second layer insulating film 50, and damp-proofing can be kept sufficiently because an inorganic film is used as a protective film 90 besides the second layer insulating film 50. Accordingly, the flattening of stepped sections and the coexistence of the increase in resistance against stress and the holding of damp proofing are enabled, thus improving the degree of integration.

7. 发明专利

JPS62171127A METHOD OF DETECTING END POINT OF ETCHING 失效
公开(公告)号：JPS62171127A
公开(公告)日：1987-07-28
申请号：JP1190386
申请日：1986-01-24
申请人： HITACHI LTD
发明人： FUKUDA TAKUYA , MISAWA YUTAKA , NAMETAKE MASATAKE
IPC分类号： H01L21/302 , H01L21/3065
摘要： PURPOSE:To detect the end point of etching with high sensitivity and accuracy, by utilizing a phenomenon that an amount of regulator reflection of unidirectional light applied onto the surface of a substance to be etched is varied by the height of a step of the surface of the substance to be etched. CONSTITUTION:Plasma is generated in an etching apparatus 3 and thereby a board to be processed is etched. In parallel with etching, a laser beam 5 of 633(nm) is applied to a desired region of a surface to be etched in the board to be processed, and regular reflection light 7 and plasma light are led into an optical filter 9 by a condenser 8. By this filter, only the desired regular reflection light 7 obtained from the laser beam 5 is separated, and a variation in the intensity thereof is detected by a light intensity detecting device 11. A light S reflected in the direction other than the direction of a desired reflection angle theta by the surface of a step (h) formed between a pattern 15 exposed on the surface by etching and a film 16 is not contained in the regulator reflection light 7, and the mount of light in the direction of the desired angle thetadecreases dependently on the step (h). Since the intensity of the regular reflection light detected from the point of time at which etchback is ended lowers sharply, the end of the etchback can be detected distinctly.

8. 发明专利

JPS6255881A COMPRESSION-BONDED TYPE MULTI-TERMINAL ASSEMBLY 失效
公开(公告)号：JPS6255881A
公开(公告)日：1987-03-11
申请号：JP19443185
申请日：1985-09-03
申请人： HITACHI LTD
发明人： INOUE KOICHI , KURIHARA YASUTOSHI , YATSUNO KOMEI , SAWAHATA MAMORU , NAMETAKE MASATAKE
IPC分类号： H01R4/02 , H01R11/01

9. 发明专利

JPS61159752A SEMICONDUCTOR RESIN PACKAGE 失效
公开(公告)号：JPS61159752A
公开(公告)日：1986-07-19
申请号：JP20485
申请日：1985-01-07
申请人： HITACHI LTD
发明人： SOGA TASAO , YATSUNO KOMEI , SAWAHATA MAMORU , NAKANO FUMIO , KOBAYASHI FUMIYUKI , NAMETAKE MASATAKE
IPC分类号： H01L23/34 , H01L23/28 , H01L23/29 , H01L23/31 , H01L23/473 , H01L25/10
摘要： PURPOSE:To obtain a high output and large-sized chip loading module pressure-contacting type semiconductor package having thermal fatigue-resistance of quintuple or more of structure, in which a bare chip is loaded, and excellent heat dissipating properties by coating the periphery of an Si chip joined onto an organic multilayer substrate having a large thermal expansion coefficient with a specific resin in specific structure. CONSTITUTION:The titled package has structure, in which the upper surfaces of chips 1 are not coated and the height of resins 12 in the periphery of the chips 1 is equalized to the upper surfaces of the chips 1 and flattened, structure, in which the height of the resins 12 is formed in a shape lower than the upper surfaces of the chips 1, or structure in which high thermal conductive plates in size larger than the chips 1 are bonded or soldered to the upper surfaces of the chips 1 in an extent that heat resistance is not increased, the upper surfaces of the high thermal conductive plates are not coated and the height of the resins 12 in the periphery of the chips 1 is made equal to or lower than the height of the upper surface of said high thermal conductive plates. The upper surfaces of the chips 1 or the upper surfaces of the high thermal conductive plates are brought into contact with a thermal conductor and cooled, or cooled through a metal and a high thermal conductive resin. A material manufactured by dispersing and mixing a low expanding material such as quartz and a granular elastic material such as rubber particles for improving the fluidity and flexibility of the resin to an epoxy resin or a polyimide resin is employed as a material for the coating resin 12.

10. 发明专利

JP2011193419A Level shift circuit and power conversion unit 有权
标题翻译：电平转换电路和电源转换单元
公开(公告)号：JP2011193419A
公开(公告)日：2011-09-29
申请号：JP2010060169
申请日：2010-03-17
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAKURAI NAOKI , SAKANO JUNICHI , NAMETAKE MASATAKE
IPC分类号： H03K19/0185 , H02M7/48 , H03K17/56
CPC分类号： H03K19/0175
摘要： PROBLEM TO BE SOLVED: To provide a level shift circuit for transmitting a control signal from a low voltage side circuit not easily giving malfunction to a high voltage side circuit even when there is a production variation in a semiconductor device during a variation in power-source voltage. SOLUTION: In the level shift circuit, when a power-source voltage variation dV/dt of a high voltage side occurs and influences on a logic level of a circuit, passing-through of a malfunction signal is masked and prevented in first and second logic circuits, by a signal from a time-constant generation circuit or a portion where a power voltage variation occurs in advance, by utilizing the fact that this variation occurs both at a set side and a reset side. When the power-source voltage variation dV/dt is generated at a high voltage side, sufficient allowance in the timing of this masking prevents an erroneous signal from being transmitted to a flip-flop, and a control signal is transmitted from a low voltage side circuit not giving malfunction to a high voltage side circuit, even when there is a production variation in each element in semiconductor processes. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种电平移位电路，用于将低电压侧电路的控制信号发送到高电压侧电路不容易产生故障，即使当在变化期间半导体器件中存在生产变化时电源电压。解决方案：在电平移位电路中，当发生高电压侧的电源电压变化dV / dt并影响电路的逻辑电平时，首先屏蔽并防止故障信号的通过和第二逻辑电路，通过利用来自设定侧和复位侧的这种变化的事实，通过来自时间常数生成电路的信号或事先发生电力电压变化的部分。当在高电压侧产生电源电压变化dV / dt时，在该掩蔽的定时中的充分允许阻止了将错误信号发送到触发器，并且控制信号从低电压侧发送电路不会对高压侧电路造成故障，即使半导体工艺中的每个元件都存在生产变化。版权所有（C）2011，JPO＆INPIT

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