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1. 发明专利

JP2006301655A Image display device 有权
标题翻译：图像显示设备
公开(公告)号：JP2006301655A
公开(公告)日：2006-11-02
申请号：JP2006138434
申请日：2006-05-18
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： AKIMOTO HAJIME , HIRAKI MITSURU , NAKAHARA HITOSHI , AKIOKA TAKASHI , KANEKO YOSHIYUKI , TSUMURA MAKOTO , MIKAMI YOSHIAKI
IPC分类号： G09G3/36 , G02F1/133 , G09G3/20 , H04N5/66
摘要： PROBLEM TO BE SOLVED: To provide an image display device without producing any problem regarding a rewriting speed.
SOLUTION: The image display device is provided with an image data input means capable of inputting at least one dynamic image data and at least one static image data to an image display section in different frame rates (>0). By dividing the image data into the dynamic image and the static image, a writing signal generating circuit 17 outputs data and address respectively. The data of the dynamic image are outputted to a dynamic image signal output circuit 43 and the address is outputted to a dynamic image vertical direction selection circuit 52 and a dynamic image horizontal direction selection circuit 44, and the data of the static image are outputted to a static image signal output circuit 41 and the address of the static image is outputted to a static image vertical direction selection circuit 51 and a static image horizontal direction selection circuit 42. It is possible that the animation or the still picture is displayed only on one part of a display pixel array.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种图像显示装置，而不会对重写速度产生任何问题。解决方案：图像显示装置具有图像数据输入装置，该图像数据输入装置能够以不同的帧速率（> 0）向图像显示部分输入至少一个动态图像数据和至少一个静态图像数据。通过将图像数据分割成动态图像和静态图像，写入信号生成电路17分别输出数据和地址。将动态图像的数据输出到动态图像信号输出电路43，并将地址输出到动态图像垂直方向选择电路52和动态图像水平方向选择电路44，并将静态图像的数据输出到静态图像信号输出电路41和静态图像的地址被输出到静态图像垂直方向选择电路51和静态图像水平方向选择电路42.可能仅在一个显示动画或静止图像上显示像素阵列的一部分。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2005202423A Image display device 有权
标题翻译：图像显示设备
公开(公告)号：JP2005202423A
公开(公告)日：2005-07-28
申请号：JP2005035405
申请日：2005-02-14
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： AKIMOTO HAJIME , HIRAKI MITSURU , NAKAHARA HITOSHI , AKIOKA TAKASHI , KANEKO YOSHIYUKI , TSUMURA MAKOTO , MIKAMI YOSHIAKI
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
摘要： PROBLEM TO BE SOLVED: To provide an image display device of super high fineness without substantially changing a rewriting speed of display pixels. SOLUTION: The image display device is provided with an image data input means capable of inputting image data in such a manner that a display pixel array 18 has two adjacent regions varying in frame rates (>0), or the display device displays the image data in an image display section constituted of the display pixel array. The image display device is constituted by being provided with an image data input means capable of inputting at least a piece of animation image data and at least a piece of still image data at the different frame rates (>0) to the image display section. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供超高细度的图像显示装置，而不显着改变显示像素的重写速度。解决方案：图像显示装置设置有能够以如下方式输入图像数据的图像数据输入装置：显示像素阵列18具有以帧频（> 0）变化的两个相邻区域，或者显示装置显示由显示像素阵列构成的图像显示部中的图像数据。图像显示装置由具有图像数据输入装置构成，该图像数据输入装置能够以不同的帧率（> 0）向图像显示部输入至少一条动画图像数据和至少一条静止图像数据。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JPH08316811A OUTPUT BUFFER CIRCUIT AND DATA PROCESSOR USING IT 失效
公开(公告)号：JPH08316811A
公开(公告)日：1996-11-29
申请号：JP11547795
申请日：1995-05-15
申请人： HITACHI LTD
发明人： AKIOKA TAKASHI , AKIYAMA NOBORU , NAMETAKE MASATAKE , IWAMURA MASAHIRO , MITSUMOTO KINYA , SHINOZAKI MASAO
IPC分类号： G06F3/00 , H03K17/12 , H03K17/14 , H03K17/16 , H03K17/567 , H03K19/003 , H03K19/0175 , H03K19/08
摘要： PURPOSE: To allow the high speed performance to be hardly affected by the environmental condition such as temperature and a power supply voltage and to reduce production of noise by supplying a prescribed current independently of the temperature and the power supply voltage to a base of a bipolar output transistor(TR) so as to drive the bipolar TR. CONSTITUTION: This output buffer circuit is provided with a constant current circuit (constant current power supplies CS1, CS2) in which bipolar TRs are employed for output TRs of a load drive circuit at the final stage of the output buffer circuit to generate a prescribed current independently of temperature and power supply voltage and allows the constant current circuit to supply a prescribed current to bases of the bipolar TRs Q1, Q2. PD1, PD2 are means to extract base charges of the output TRs Q1, Q2. Thus, the current supplied to the output TRs Q1, Q2 is a constant current independently of the temperature and the power supply voltage, and then dispersion in a delay time of the output buffer circuit under the environment of using an LSI is very small.

4. 发明专利

JPH06314499A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH06314499A
公开(公告)日：1994-11-08
申请号：JP20637293
申请日：1993-08-20
申请人： HITACHI LTD
发明人： AKIYAMA NOBORU , MITSUMOTO KINYA , AKIOKA TAKASHI , NAMETAKE MASATAKE
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04 , G11C29/24
摘要： PURPOSE:To relieve the block even if defects are concentrated in a specified block. CONSTITUTION:When no defect exists in the column relief unit array 211 of a memory block 200, a pre-sense amplifier 220 is turned on and a signal from a designated data line 341 is outputted through the pre-sense amplifier. On the other hand, when a defect arises in the column relief unit array, the pre- sense amplifier is turned off and the output of the signal from the data line 341 is inhibited. Instead, a redundant pre-sense amplifier 220R in a redundant memory block 310 is turned on and a signal from a redundant data line 341R is outputted from the redundant pre-sense amplifier to an I/O line selecting circuit 3000. The correspondence of the defective column relief unit array with a redundant column relief unit array 311 is performed in the I/O line selecting circuit 3000. Namely, the data of redundant column relief unit array 311 are outputted instead of the data of the defective column relief unit array.

5. 发明专利

JPH05235736A 失效
公开(公告)号：JPH05235736A
公开(公告)日：1993-09-10
申请号：JP3036792
申请日：1992-02-18
申请人： HITACHI LTD
发明人： TANIFUJI SHIYUUKO , AKIOKA TAKASHI , TANBA AKIHIRO , NAMETAKE MASATAKE , KOBAYASHI YUTAKA
IPC分类号： G11C11/41 , H03K19/01 , H03K19/0175 , H03K19/08
摘要： PURPOSE:To increase the operating speed by providing a high drive capability without increasing an input capacity of a multi-input logic gate circuit to reduce the delay time. CONSTITUTION:At least one MOS transistor(TR) is employed for components at an output stage and logic circuits G1, G2 are provided to a pre-stage to differentiate independently the logic threshold level of the G1, G2 thereby controlling the switching speed of output stages S1, S2, and the gate of the S2 is set independently of the input capacitance of the logic circuits G1, G2, then the S2 is increased to lower the ON-resistance. Through the constitution above, the delay time is reduced and the output amplitude is surely swung up to a voltage V2, the gate with a small layout area is obtained and the operating speed of the semiconductor device is improved.

6. 发明专利

JPH03216892A SEMICONDUCTOR MEMORY AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH03216892A
公开(公告)日：1991-09-24
申请号：JP1094690
申请日：1990-01-20
申请人： HITACHI LTD
发明人： YAMAUCHI TATSUMI , IWAMURA MASAHIRO , AKIOKA TAKASHI , HIRAISHI ATSUSHI , YOKOYAMA YUJI , KOBAYASHI YUTAKA , IDE AKIRA
IPC分类号： G11C11/417 , G11C11/409
摘要： PURPOSE:To shorten the time of data write to a memory cell by cutting off the data line of the selected memory cell and a common read line at the time of writing data in the memory cell. CONSTITUTION:Data lines of memory cells of plural columns which are omitted in the figure are connected to a common read line 10 and a common write line 11 through read transfer gates 103(M3) and 104(M4) and write transfer gates 101(M1) and 102(M2). Consequently, read transfer gates 103(M3) and 104(M4) can be forcibly turned off by a write control signal the inverse of w, and data written in a pair of data lines D and the inverse of D is not propagated to the common read line 10 at the time of data write. That is, since the potential of the common read line is not changed by data write, the overall capacity charged to and discharged from a load is reduced at the time of write to shorten the write time.

7. 发明专利

JPH03105799A REDUNDANCY MEMORY DEVICE AND DEFECT MEMORY RELIEVE SYSTEM 失效
公开(公告)号：JPH03105799A
公开(公告)日：1991-05-02
申请号：JP24212589
申请日：1989-09-20
申请人： HITACHI LTD
发明人： AKIOKA TAKASHI , YOKOYAMA YUJI , HIRAISHI ATSUSHI , IWAMURA MASAHIRO , KOBAYASHI YUTAKA , YAMAUCHI TATSUMI , TAKAHASHI SHIGERU , MOTOHASHI KOICHI
IPC分类号： G11C29/00 , G11C11/401 , G11C29/04
摘要： PURPOSE:To quicken the access to a redundant memory cell by providing a means generating an access inhibit signal and a means selecting a standby memory cell array when a defect memory cell in a block is accessed to each of plural blocks. CONSTITUTION:An address signal 8 outputted from an address buffer 1 designates an address of a memory cell of a memory cell array 4 of each block. The position of a defect memory cell provided to a prestage of an X decoder 2 and a Y decoder 5 is programmed and inputted to a redundancy program circuit 6. When the address of the defect memory cell is inputted, the redundancy program circuit 6 inputs a defect memory cell access suppression signal to the Y decoder 5 to suppress the access of the defect memory cell. Moreover, a redundancy memory cell array access signal selecting a redundancy memory cell array 7 is generated in the redundancy program circuit 6 to relieve the defect memory. Thus, the accessing to the redundancy memory cell is quickened.

8. 发明专利

JPH02186676A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02186676A
公开(公告)日：1990-07-20
申请号：JP493689
申请日：1989-01-13
申请人： HITACHI LTD
发明人： AKIOKA TAKASHI , NAGANO TAKAHIRO , HONMA HIDEO
IPC分类号： H01L29/78
摘要： PURPOSE:To reduce a parasitic capacitance between a channel region and a substrate through punch-through independent of breakdown strength by a method wherein the channel region and the substrate of a vertical MOSFET are isolated from each other by an insulating layer. CONSTITUTION:A drain 1 and a channel region 2 are isolated from a substrate 8 with an insulating layer 7. When a positive voltage, for instance, of 5V is applied to a gate electrode 4, a voltage of 0V is applied to a source electrode 5, and a positive voltage, for instance, of 5V to a drain electrode 6, a channel is formed along a gate insulating film inside the channel region 2 and a drain current flows. Next, when a voltage of 0V is applied onto the gate electrode 4, the above channel dissipates and the drain current is turned OFF. By this setup, a channel region by which a MOSFET is influenced in characteristics is connected in crystal with the single crystal Si of high quality of a substrate, so that the channel region is easy to crystallize high in quality and an SOI MOS FET of high performance can be obtained.

9. 发明专利

JPH01196160A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01196160A
公开(公告)日：1989-08-07
申请号：JP1965588
申请日：1988-02-01
申请人： HITACHI LTD
发明人： AKIOKA TAKASHI , WATANABE TOKUO , SAWAHATA YASUO , NAGANO TAKAHIRO , KAWAKAMI SUMIO
IPC分类号： H01L21/28 , H01L21/331 , H01L21/8228 , H01L27/08 , H01L27/082 , H01L29/72 , H01L29/73 , H01L29/732
摘要： PURPOSE:To secure a good high-frequency characteristic and a required breakdown strength value by a method wherein a second conductor layer which is connected, in an ohmic manner, to the side face of a first conductor layer used both to position an emitter and a collector while it is situated between them and to be extracted to a base electrode and whose width is controlled is formed in a self-aligned manner. CONSTITUTION:A first conductor layer 8 used to position an interval between an emitter region 5 and a high-concentration collector region 4 is formed; a second conductor layer 60 connected to the layer in an ohmic manner is formed at the side face. Because the N-type polycrystalline silicon 80 can be formed in a self-aligned manner with reference to the first conductor 8, the contact area of a base region 3 required to interlink the first conductor layer 6 with the base region 3 is reduced sharply. On the other hand, because the first conductor layer 6 decides an interval between the emitter and base regions 5, 3 and the P type high-concentration collector region 4, its length can be set appropriately in correspondence to a required breakdown strength value. During this process, the width of the N-type polycrystalline silicon 80 has nothing to do with the length of the first conductor layer 8; accordingly, the contact area with reference to the base region 3 is not changed, and a high-frequency characteristic is not influenced adversely.

10. 发明专利

JP2002190532A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JP2002190532A
公开(公告)日：2002-07-05
申请号：JP2000386087
申请日：2000-12-19
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： UENO YOUKI , AKIOKA TAKASHI , MITSUMOTO KINYA , AOYAMA AKIHISA , SHINOZAKI MASAO
IPC分类号： G11C11/41 , G11C7/10 , G11C7/18 , G11C11/419 , H01L21/8244 , H01L27/11
摘要： PROBLEM TO BE SOLVED: To reduce parasitic capacitance formed between a bit line for reading out the signal of a memory cell and a signal transmission line disposed on the upper layer thereof. SOLUTION: Complementary second global bit lines (GBL, /GBL) for transmitting the data of a memory cell MC, read out through complementary bit lines (BL, /BL), are disposed above a memory cell array (BLock). The second global bit line (GBL or /GBL) is disposed, such that an isosceles triangle is defined by connecting the center of cross-section of one complementary bit line (BL), the center of cross-section of the other complementary bit line (/BL), and the center of cross-section of the second global bit line (GBL or /GBL) disposed directly above these complementary bit lines (BL, /BL).

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