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1. 发明专利

JPS6237954A LEAD FRAME FOR GLASS SEALED TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6237954A
公开(公告)日：1987-02-18
申请号：JP17739885
申请日：1985-08-12
申请人： HITACHI CABLE , HITACHI LTD
发明人： SANKI SADAHIKO , SATO JUNICHI , ONDA MAMORU , IIZUKA TOMIO , EMOTO YOSHIAKI , TSUCHIDA MINORU
IPC分类号： H01L23/02 , H01L23/48 , H01L23/50
摘要： PURPOSE:To prevent cracking of sealing glass, by providing roundness having a required radius of curvature at the peripheral part of a lead part after blanking, thereby removing stress concentration to the peripheral part of the lead part. CONSTITUTION:The cross sectional shape of a lead part 8 of a part sealed with sealing glass 3 is made to be an approximately rectangular shape by chemical polishing and the like as a whole. The lead part is formed by a flat part, which has a width of 50mum or more and is used for wire bonding, and a peripheral part, which has roundness with the radius of curvature of 0.2mum or more. Then, thermal stress is not concentrated to the sealing glass, which is closely contacted with the lead part 8. Thus, cracking of the sealing glass can be prevented.

2. 发明专利

JPH01272140A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01272140A
公开(公告)日：1989-10-31
申请号：JP10030988
申请日：1988-04-25
申请人： HITACHI LTD
发明人： EMOTO YOSHIAKI , OTSUKA KANJI , YATSUNO KOMEI , KURIHARA YASUTOSHI , MIWA TAKASHI , KURODA SHIGEO , OKUYA KEN , YAMADA TAKEO , SAWARA KUNIZO , KOBAYASHI TSUNEO , SATO TOSHIHIKO , SHIRAI MASAYUKI
IPC分类号： H01L23/538 , H01L23/08 , H01L23/14 , H01L23/15 , H01L23/52
摘要： PURPOSE:To manufacture various packages having excellent heat-dissipating properties and high reliability by using an aluminum nitride substrate capable of forming a multilayer substrate through a green sheet method as a package base and mounting and sealing a cap composed of aluminum nitride or mullite onto the base by a sealing medium. CONSTITUTION:A package 1 consists of AlN, AlN powder is kneaded with a liquefied binder, CaCO3, etc., and a green sheet is manufactured, and a required number of the green sheets are superposed, and contact-bonded and sintered. Through-holes are bored to the green sheets by a press, patterns are printed, and internal wirings 2 conducting superposition sintering can be shaped. Multilayer thin-film circuits are formed by an insulating layer 3A and thin-film conductors 3B on the surface of a base 1 in a thin-film multilayer interconnection 3. An AlN film and a polyimide synthetic resin may also be used as the insulating layer 3A, but it is preferable that thin film diamond through a vapor phase method is employed. A cap made up of AlN or mullite is fitted, thus eliminating the need for a water cooling jacket on the cap.

3. 发明专利

JPH01194439A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01194439A
公开(公告)日：1989-08-04
申请号：JP1980488
申请日：1988-01-29
申请人： HITACHI LTD
发明人： UDA TAKAYUKI , TANAKA TAMOTSU , EMOTO YOSHIAKI , KURODA SHIGEO
IPC分类号： H01L21/28 , B23K1/00 , H01L21/306 , H01L21/3205 , H01L21/321 , H01L21/60
摘要： PURPOSE:To improve the exfoliation of a region not formed with a conductor film of a second resist film by forming an opening formed with a dummy conductor film on a region not formed with the conductor film in a first resist film disposed on a substrate and a second resist film formed on a conductor film forming region, and invading an exfoliation solution on the second film through the opening. CONSTITUTION:A first resist film 18 is formed on a passivation film 4I of a region not formed with a salient-electrode (conductor film) 8 of a mother chip 4. Then, a second resist film 19 is formed on a whole substrate including the film 4I and the film 18. Thereafter, a first opening 20A is formed at a part formed with the electrode 8 of the film 19 (on an inner terminal P1), and a second opening 20B for forming a dummy salient-electrode 8A is formed on a region not formed with the electrode 8. The electrode 8 is formed on a barrier metal layer 4K on wirings 4G of the inner terminal P1 in the opening 20A of the film 19. An exfoliation solution is impregnated to the film 19 through the opening 20B. Then, the films 19, 18 are removed. Since the film 18 can be removed in the step of removing the film 19, manufacturing steps can be shortened.

4. 发明专利

JPS61125024A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS61125024A
公开(公告)日：1986-06-12
申请号：JP24598484
申请日：1984-11-22
申请人： Hitachi Ltd
发明人： EMOTO YOSHIAKI , ISHIDA TAKASHI , OTSUKA KANJI , FURUKAWA MICHIAKI , KOBAYASHI TSUNEO
IPC分类号： H01L23/15 , H01L21/52 , H01L21/58 , H01L23/14
CPC分类号： H01L24/83 , H01L24/26 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/8319 , H01L2224/8385 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/15153 , H01L2924/15165 , H01L2924/16152 , H01L2924/00014
摘要： PURPOSE:To allow a semiconductor device to operate at a high speed, by providing a fluorine resin film or wiring on a substrate for putting semiconductor chips thereon, and then a wiring or fluorine resin film on the surface of the fluorine resin or wiring. CONSTITUTION:On a package substrate made of SiC containing a small amount of beryllia, wirings 2 and outward lead wires 3 are provided. The package substrate 1 has a recess at the central section, in which a semiconductor sub strate 4 for putting semiconductor chips thereon is bonded. A plural of semicon ductor chips 5 are put on the mother substrate 4 through projection electrodes 6 such as soldering bumps of a flip-chip type. A package cap 8 is bonded to the package substrate 1 with adhesive to seal semiconductor chips 5, etc. In this construction, by providing with a signal wiring 13 on an insulating layer 11 made of fluorine resin with a low dielectric constant, the distance between the power source or ground wiring 9 and the signal wiring 13 can be made long in order to reduce the capacity across them. Moreover, since the insulating layer has such a low dielectric constant, the semiconductor device can be operat ed at a fast speed.
摘要翻译：目的：为了使半导体器件能够高速运转，通过在其上放置半导体芯片的基板上设置氟树脂膜或布线，然后在氟树脂或布线的表面上配置布线或氟树脂膜。构成：在由含有少量氧化铍的SiC制成的封装衬底上，配线2和外引线3。封装基板1在中心部分具有凹部，其中结合用于将半导体芯片放置在其上的半导体基板4。多个半导体芯片5通过诸如倒装芯片型焊接凸起的投影电极6放置在母基板4上。封装帽8用粘合剂粘合到封装衬底1上以密封半导体芯片5等。在这种结构中，通过在由低于介电常数的氟树脂制成的绝缘层11上设置信号布线13，可以使电源或接地布线9以及信号布线13变长，以便减小它们的容量。此外，由于绝缘层具有如此低的介电常数，所以半导体器件可以以快速的速度工作。

5. 发明专利

JPS60198758A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60198758A
公开(公告)日：1985-10-08
申请号：JP5420884
申请日：1984-03-23
申请人： HITACHI LTD
发明人： EMOTO YOSHIAKI , OOTSUKA KANJI , KOBAYASHI TSUNEO
IPC分类号： H01L23/36 , H01L23/15 , H01L23/373 , H01L23/538
摘要： PURPOSE:To accomplish efficient heat dissipation by a method wherein a multilayer wiring layer is formed over one surface of a substrate having a high thermal conductivity and almost the same coefficient of thermal expansion as that of a chip provided thereon, and a chip is mounted on the opposite surface, both of which are then connected with through hole wirings. CONSTITUTION:A substrate 1 of silicon carbide formed by hot press and containing 0.1-3.5wt% of beryllium of high thermal conductivity is provided with the through hole wirings 2 penetrating through this substrate in the thickness direction thereof. The through hole wiring 2 electrically connects the multilayer wiring layer 3 formed on the back of the substrate 1 to the chip 8 mounted on the front of the substrate 1. Signal wirings 4 and power source wirings 5 are connected to installation electrodes 6 to install the chip 8 respectively via through hole wiring 2. Many chips 8 are installed to the installation electrodes 6 with connection bumps 9. A forced cooling member 10 is provided so as to surround the side surface of the substrate 1.

6. 发明专利

JPS6020522A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6020522A
公开(公告)日：1985-02-01
申请号：JP12763183
申请日：1983-07-15
申请人： HITACHI LTD
发明人： ISHIDA TAKASHI , SEKI MASATOSHI , SAWARA KUNIZOU , EMOTO YOSHIAKI , KAMATA CHIYOSHI
IPC分类号： H01L21/60
摘要： PURPOSE:To obtain a wiring, dimensional accuracy thereof is high and resistance thereof is low, by forming the wiring on a package substrate by multilayer wiring consisting of titanium and copper. CONSTITUTION:A wiring 4 is formed as three layer thin-film multilayer wirings consisting of a titanium layer 10 formed on a package substrate 11 after sinterings through the evaporation of a thin-film, a copper layer 11 evaporated on the layer 10 in a thin-film shape and a titanium layer 12 evaporated on the layer 11 in the thin-film shape. A pedestal section 5 is composed of a copper layer 13 evaporated on the titanium layer 12 as the uppermost layer of the wiring 4 in the thin-film shape and a titanium layer 14 evaporated around the copper layer 13 in the thin-film shape. Since the wiring 4 is formed by the three layer thin- film evaporated layers of the titanium layer 10, the copper layer 11 and the titanium layer 12, the wiring 4 and the pedestal section 5 are formed with dimensional accuracy higher than a tungsten wiring formed through sintering. Accordingly, a large-sized pellet can be face-down bonded. The resistance of the wiring 4 can be lowered by the presence of the copper layer 11.

7. 发明专利

JPH03171643A JOINTING OF METAL MEMBER, METHOD AND DEVICE FOR MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING SAME 失效
公开(公告)号：JPH03171643A
公开(公告)日：1991-07-25
申请号：JP30992289
申请日：1989-11-29
申请人： HITACHI LTD
发明人： NAKAO TAKASHI , EMOTO YOSHIAKI , SEKIGUCHI KOICHIRO , IKETANI MASAYUKI , SAWARA KUNIZO , YOSHIDA IKUO , KONO AKIOMI
IPC分类号： H01L21/60 , H01L23/12
摘要： PURPOSE:To reduce heat damage to a semiconductor chip and to realize a reduction in a reflow time and a reduction in the size of a reflow furnace by a method wherein an atomic beam or an ion energy beam is irradiated on the joint surfaces of a pair of metal members housed in a vacuum container and thereafter, the metal members are transferred to a container, in which a high-purity inert gas-containing atmosphere is formed, and the joint surfaces of the metal members are pressure-welded to each other under normal pressures. CONSTITUTION:A pair of source guns 18 for transforming Ar gas introduced in a surface activating chamber 17 into an atom beam are installed in the chamber 17 and a semiconductor chip 5 and a package substrate 3 are irradiated with this atomic beam. Thereby, an activating treatment is performed on the surfaces of CCB bumps 2 and electrodes 4. After that, the chip 5 and the substrate 3 are immediately transferred to a jointing chamber 20 as they are respectively housed in trays 15a and 15b through a second load-lock chamber 19. A high-purity inert gas-containing atmosphere of normal pressures is formed in the chamber 20. A temporary jointing mechanism and a fusion jointing mechanism are provided in the interior of the chamber 20 and the temporary jointing and the final jointing are performed using these mechanisms.

8. 发明专利

JPH01217951A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01217951A
公开(公告)日：1989-08-31
申请号：JP4199688
申请日：1988-02-26
申请人： HITACHI LTD
发明人： EMOTO YOSHIAKI , UDA TAKAYUKI , TANAKA TAMOTSU , KURODA SHIGEO
IPC分类号： H01L23/36 , H01L23/46 , H01L23/473
摘要： PURPOSE:To surely prevent the deformation of a CCB bump due to the load of a heat dissipating body, by mounting a pellet, on the upper surface of which the heat dissipating body is arranged, on a substrate via the CCB bump, and making a spacer interpose between the substrate and the pellet or between the substrate and the heat dissipating body. CONSTITUTION:A sphere type CCB bump 6 composed of solder material is connected between the electrode 4 of a pellet 2 and the electrode 5 of a multilayer board 1, and an integrated circuit of the pellet 2 and a wiring of the multilayer board 1 are electrically connected via the CCB bump 6. On the surface of the multilayer board 1, rectangular frame type spacer 7 composed of material with high thermal conductivity is interposed on the periphery of the pellet 2, and joined to the surface of the multilayer board 1 via solder material 8. An expanded heat dissipating plate 9 of a rectangular plate type having an external diameter nearly equal to the pellet 2 is joined to the upper surface of the pellet 2 via solder material 10. A little gap (d) is formed between the upper surface of the spacer 7 and the periphery of the lower surface of the expanded heat dissipating plate 9. A first heat sink 11 and a second heat sink 12 are mounted on the upper surface of the expanded heat dissipating plate 9.

9. 发明专利

JPH01194443A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01194443A
公开(公告)日：1989-08-04
申请号：JP1980588
申请日：1988-01-29
申请人： HITACHI LTD
发明人： UDA TAKAYUKI , TANAKA TAMOTSU , EMOTO YOSHIAKI
IPC分类号： H01L21/60
摘要： PURPOSE:To shield a salient-electrode from an alpha-ray and to reduce a variation in the threshold voltage of a complementary MISFET by forming an alpha-ray shielding film on the complementary MISFET forming region of a semiconductor chip when the element is formed by a lift-off technique on a bipolar transistor forming region. CONSTITUTION:In the region of a memory circuit RAM of a mixed semiconductor chip 21 having a bipolar transistor and a complementary MISFET and/or the region of a circuit formed of a complementary MISFET, an alpha-ray shielding film 22 is formed on a passivation film 21AB. The film 22 is so formed as to shield an alpha-ray radiated from a radioactive element (U, Th) generation source containing a small amount mainly in a salient-electrode 8. The film 22 is formed of a polyimide series resin film, such as a polyimide-isoindoloquinazolinedione film. The film 22 is formed on a region except a region formed with the electrode 8. Since the film 22 has different thermal expansion coefficient from that of the semiconductor substrate 21A of the chip 21, the film 22 is not brought into contact with the electrode 8 due to the damage or breakdown of the electrode 8 by a thermal stress.

10. 发明专利

JPS62224099A MULTILAYER INTERCONNECTION BOARD AND MANUFACTURE OF THE SAME 失效
公开(公告)号：JPS62224099A
公开(公告)日：1987-10-02
申请号：JP6577686
申请日：1986-03-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： EMOTO YOSHIAKI , SUGIMOTO SHUICHI , SHIRAI MASAYUKI
IPC分类号： H05K3/46

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