专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH05315400A BONDER FOR ELECTRONIC CIRCUIT DEVICE 失效
公开(公告)号：JPH05315400A
公开(公告)日：1993-11-26
申请号：JP11916592
申请日：1992-05-12
申请人： HITACHI LTD
发明人： SAKATA TOMOAKI , ODAJIMA HITOSHI , TANAKA KATSUHISA , MURASE TOMOHIKO , SATO RYOHEI , NISHIKAWA TORU , KONO AKIOMI , HORINO MASAYA , HAYASHIDA TETSUYA , SAWARA KUNIZO
IPC分类号： H01L21/60
摘要： PURPOSE:To improve reliability and producibility of solder bonding of an electronic circuit device which is bonded without using flux by providing a loader part, an unloader part and each treatment chamber with a carrier means which can receive a part and a tray from a preceding process and deliver them to a following process. CONSTITUTION:A loader part 1 which supplies a tray whereon a plurality of parts to be bonded are mounted at a unit of each tray and a surface cleaning chamber 2 which is held varuum, removes a coatiang of a surface of the parts to be bonded of each part and carries them to a following process are provided. An alignment chamber 3 is also provided which pressurizes and joints a position detection part which detects position relation of a bonding part of each part and the bonding part of each part charged with a specified pressure of nonoxidizing atmosphere after alignment and carries the jointed parts to a following process. An unloader part 5 for carrying out the jointed parts and load lock chambers 6, 7, 8 for matching atmosphere between parts are provided.

2. 发明专利

JPH04160357A QUANTITATIVELY MEASURING APPARATUS FOR PARTIAL PRESSURE OF GAS 失效
公开(公告)号：JPH04160357A
公开(公告)日：1992-06-03
申请号：JP28425890
申请日：1990-10-24
申请人： HITACHI LTD
发明人： KONO AKIOMI , HORINO MASAYA , KANAMARU MASATOSHI , SAWARA KUNIZO
IPC分类号： G01L21/30 , C23C14/54 , G01N27/62 , H01J49/42
摘要： PURPOSE:To calibrate a quadruplex electrode mass analyser using gas of known concn. by setting an analyzing chamber and a piping system to the background of an ultrahigh vacuum region. CONSTITUTION:At first, an analyzing chamber 2 and respective pipings are evacuated up to an ultrahigh vacuum region (10 Torr or less) before analysis. Next a valve 9 is opened and gas of known concn. is introduced into the analyzing chamber 2 from a standard gas cylinder 3 until the pressure in the analyzing chamber 2 due to an ionizing vacuum meter 10 becomes 1X10 Torr. A quadruplex electrode analyser (QMS) 4 is operated to measure the partial pressures of the respective gases in the standard gas. After the pressure in the analyzing chamber 2 reaches the level of 10 Torr, a valve 12 is opened and the residual gas in the pipings is discharged until the ionizing vacuum meter 13 shows the level of 10 Torr. Thereafter, the gas in a container 1 is introduced into the analyzing chamber 2 to set the pressure in the analyzing chamber 2 to 1X10 Torr. Then, the gas is analyzed by the QMS 4 and the analyzed result is calibrated on the basis of a previously calculated correction factor by a personal computer 7.

3. 发明专利

JPH03203255A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03203255A
公开(公告)日：1991-09-04
申请号：JP34423989
申请日：1989-12-28
申请人： HITACHI LTD
发明人： SAWARA KUNIZO , KIKUCHI HIROSHI , SATO TOSHIHIKO , HAYASHIDA TETSUYA
IPC分类号： H01L23/02
摘要： PURPOSE:To reduce the generation of leak at a sealed section and improve hermetical sealing performance in a cap by including a high melting point solder within solder in a sealing section. CONSTITUTION:High melting point solder 7, which has a higher melting point than that of back side solder, is applied in a ring shape in a gap at a sealing section between a base 3 and a cap 4. Solder 6 at the sealing section melts in such a manner that it envelops the high melting point solder 7. The high melting point solder 7 does not melt easily since it has a high melting point and remain unmelted in the gap of the sealing section. Furthermore, since the high melting point solder is contained therein, the sealing section solder 6 reduces its thickness at the sealing section so that the thickness of the sealing section solder 6 present between the high melting point solder 7 and the base 3 and the cap 4 is reduced to 10 to 20mum. This thickness is smaller than the size of solder crystal. Therefore, no cavity is generated in the sealing section during solidification, thereby improving the hermetical sealing performance.

4. 发明专利

JPH03171643A JOINTING OF METAL MEMBER, METHOD AND DEVICE FOR MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING SAME 失效
公开(公告)号：JPH03171643A
公开(公告)日：1991-07-25
申请号：JP30992289
申请日：1989-11-29
申请人： HITACHI LTD
发明人： NAKAO TAKASHI , EMOTO YOSHIAKI , SEKIGUCHI KOICHIRO , IKETANI MASAYUKI , SAWARA KUNIZO , YOSHIDA IKUO , KONO AKIOMI
IPC分类号： H01L21/60 , H01L23/12
摘要： PURPOSE:To reduce heat damage to a semiconductor chip and to realize a reduction in a reflow time and a reduction in the size of a reflow furnace by a method wherein an atomic beam or an ion energy beam is irradiated on the joint surfaces of a pair of metal members housed in a vacuum container and thereafter, the metal members are transferred to a container, in which a high-purity inert gas-containing atmosphere is formed, and the joint surfaces of the metal members are pressure-welded to each other under normal pressures. CONSTITUTION:A pair of source guns 18 for transforming Ar gas introduced in a surface activating chamber 17 into an atom beam are installed in the chamber 17 and a semiconductor chip 5 and a package substrate 3 are irradiated with this atomic beam. Thereby, an activating treatment is performed on the surfaces of CCB bumps 2 and electrodes 4. After that, the chip 5 and the substrate 3 are immediately transferred to a jointing chamber 20 as they are respectively housed in trays 15a and 15b through a second load-lock chamber 19. A high-purity inert gas-containing atmosphere of normal pressures is formed in the chamber 20. A temporary jointing mechanism and a fusion jointing mechanism are provided in the interior of the chamber 20 and the temporary jointing and the final jointing are performed using these mechanisms.

5. 发明专利

JPH0368163A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0368163A
公开(公告)日：1991-03-25
申请号：JP16398289
申请日：1989-06-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OTSUKA KANJI , KATO MASAO , USAMI MITSUO , KURODA SHIGEO , KUMAGAI TAKASHI , SAWARA KUNIZO , YAMADA TAKEO , OKINAGA TAKAYUKI , MIYAMOTO SEIJI , SHIRAI MASAYUKI , KUBO KAZUHISA , TATE HIROSHI , KAWASHIMA MASAYUKI
IPC分类号： G01R31/26 , G01R1/073 , H01L21/60 , H01L23/08 , H01L23/12 , H01L23/473 , H01L23/50 , H01L25/04 , H01L25/18 , H05K3/34
摘要： PURPOSE:To protect a connection part between a lead and a package against breakage by a method wherein the deformation strength of the lead which connects a package provided with a semiconductor chip inside it to an electrode is made smaller than the joining strength of a joint between the lead and the electrode. CONSTITUTION:A large number of electrodes 3 connected to a multilayered wiring 14B provided inside a printed wiring board 1 are arranged on the surface of the printed wiring board 1 at a prescribed interval. A microchip carrier 2 is possessed of a package structure composed of an insulating board 4 and a cap 5 and a semiconductor chip 6 is hermetically enveloped in the carrier 2. A large number of electrodes 8 are arranged in gridirons on the whole underside of the board 4 and connected to the upper electrodes 3 through the intermediary of a wiring 14A which runs through the inside of the insulating board 4. The upper ends of lead pins 11 are joined to the lower electrodes 8 of the board 4 through the intermediary of bonding agent 12, and the lower ends of the pins 11 are connected to the electrodes 3 through the intermediary of solders 13. The lead pin 11 is so designed as to make its bending strength to a compression load applied in an axial direction smaller than both the bonding strengths of the bonding agent 12 and the solder 13.

6. 发明专利

JPS63293931A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS63293931A
公开(公告)日：1988-11-30
申请号：JP12828587
申请日：1987-05-27
申请人： HITACHI LTD
发明人： SAWARA KUNIZO , OTSUKA KANJI , ISHIDA TAKASHI
IPC分类号： H01L23/34 , H01L21/60
摘要： PURPOSE:To improve remarkably heat dissipation characteristics, by performing the heat dissipation from a semiconductor region in which heat dissipation bump is used, via an insulating film composed of diamond having superior thermal conductivity. CONSTITUTION:A diamond thin film 11 is formed on the surface of a mother chip 1. A heat dissipating bump 9 is fixed on the diamond thin film 11 via a bonding metal 12, and connected to a sub-chip 3. A heat dissipating fin 16 is fixed on the surface of a substrate 2 opposite to the surface on which the mother chip 1 is fixed. The diamond thin film 11 is preferably formed by electron beam CVD method. The heat generated from a semiconductor active region 17 of the sub-chip 3 is dissipated through the diamond insulating film 11, the heat dissipating bump 9, the mother chip 1, the substrate 2 of a package, and the heat dissipating fin 16. As the thermal conductivity of the diamond thin film 11 is superior, a multichip module whose heat dissipation characteristics are excellent can be obtained.

7. 发明专利

JPS63239826A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63239826A
公开(公告)日：1988-10-05
申请号：JP7140787
申请日：1987-03-27
申请人： HITACHI LTD
发明人： SAWARA KUNIZO , KURODA SHIGEO , OTSUKA KANJI , YAMADA TAKEO
IPC分类号： H01L21/60 , H01L23/12
摘要： PURPOSE:To prevent the deterioration of moisture resistance resulting from a contaminant on the outside, and to improve reliability by filling a section between a semiconductor chip and a substrate for loading with silicone gel and forming a member for obviating the flow of silicone gel onto the mounting surface of the substrate for loading in the peripheral section of the semiconductor chip. CONSTITUTION:A section between a semiconductor chip 1 and a substrate 3 for loading is filled with silicone gel 4 hermetically sealing external terminals for the semiconductor chip 1, bump electrodes 2 and the substrate 3 for loading. A member 5 for preventing a flow is shaped to the peripheral section of the semiconductor chip 1 on the mounting surface of the substrate 3 for loading. The member 5 for preventing the flow is formed by a thin-film such as a polyimide resin thin-film, and constituted so as to be made lower than the height of the rear of the semiconductor chip 1 loaded onto the substrate 3 for loading. Consequently, when the silicone gel 4 is cast, an outflow onto the mounting surface of the substrate 3 for loading of the silicone gel 4 is obviated, thus ensuring a fill of the silicone gel 4, then allowing hermetic seal. Accordingly, the moisture resistance of a semiconductor device can be improved, thus enhancing reliability.

8. 发明专利

JPS6379330A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6379330A
公开(公告)日：1988-04-09
申请号：JP22360986
申请日：1986-09-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： UCHIUMI YASUYUKI , SHIRAI MASAYUKI , OKINAGA TAKAYUKI , SAWARA KUNIZO , OTSUKA KANJI
IPC分类号： H01L21/52 , H05K3/24 , H05K3/34 , H05K3/40
摘要： PURPOSE:To improve the life of a connection part, by arranging, on the surface of a mounting substrate, a metal pillar-shaped body having a melting point higher than a projection electrode, and connecting a semiconductor element having the projection electrode and the metal pillar-shaped body by controlled collapse bonding. CONSTITUTION:After a film resist 2 is laminated on the surface of a mounting substrate 1, a lot of holes reaching the substrate surface are formed in the resist 2. In the inside of holes of the resist 2, a metal like copper is supplied to form a pillar-shaped body 4, on which and Ni layer 7 and an Au layer 8 are laminated. After that, the resist 2 is eliminated. Solder bump in the form of a semisphere of the projection electrode 5 of a semiconductor element 6 is melted by a solder reflow method, and the element 6 and the substrate 1 are connected by controlled collapse bonding.

9. 发明专利

JPS634653A WIRING SUBSTRATE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS634653A
公开(公告)日：1988-01-09
申请号：JP14690686
申请日：1986-06-25
申请人： HITACHI LTD
发明人： SATO TOSHIHIKO , OTSUKA KANJI , SAWARA KUNIZO , YAMADA TAKEO , TANAKA TAMOTSU , OKUYA KEN , KURODA SHIGEO , TAKEO YOSHIHISA , KOBAYASHI TSUNEO , HIOKI SUSUMU
IPC分类号： H01L23/522 , H01L21/768 , H01L23/12 , H01L23/14
摘要： PURPOSE:To prevent the generation of deformation such as warpage in a wiring substrate, and to connect an electronic part such as a semiconductor chip and the wiring substrate electrically and positively by forming a diffused junction layer near a through-wiring. CONSTITUTION:A semiconductor substrate 10 is etched to shape grooves 10A, insulating films 11 are formed onto both the surface and the back and grooves 11A are shaped. Wirings 12 are formed in the groove sections 11A, thus shaping a first laminate 13. A plurality of the first laminates 13 are superposed between semiconductor substrates 14, and diffused junction layers 16 shown in dotted lines are formed on joint surfaces 15 by using a solid diffused junction technique. Accordingly, the semiconductor substrates 14, the first laminates 13, the next first laminates 13 and the further next laminate 13 are each joined firmly without generating deformation such as warpage, thus forming a second laminate 17, then ensuring electric connections.

10. 发明专利

JPS61148826A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61148826A
公开(公告)日：1986-07-07
申请号：JP27083084
申请日：1984-12-24
申请人： HITACHI LTD
发明人： SAWARA KUNIZO , OTSUKA KANJI
IPC分类号： H01L21/58
摘要： PURPOSE:To extremely reduce the delay time of signal transmission speed by forming wirings of one or more layers aerially partially supported at required positions on a substrate. CONSTITUTION:A mother chip provides a wiring 12 for signal aerially supported by a strut made of copper at a required position on a silicon substrate 3a. Consequently, the wiring 12 is surrounded with air which has relative permitivity of approx. 1 and the delay time of signal transmission speed in the wiring 12 can be made extremely small. A ground layer 13 is formed on nearly all the surface of the silicon substrate 3a and the distance wherein the line of electric force of the wiring 12 affects is made extremely small so that delay time can also be made small.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式