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1. 发明专利

JPS55163698A MEMORY PROTECTING SYSTEM 失效
公开(公告)号：JPS55163698A
公开(公告)日：1980-12-19
申请号：JP7098579
申请日：1979-06-06
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD , FUJITSU LTD
发明人： YASUMI NAOAKI , SEIJI TAKAYUKI , SHIOKAWA SHIZUO , SUMIMOTO TSUTOMU , OOKAWA MASAYUKI
IPC分类号： G06F12/14 , G06F12/08 , G06F12/10 , G06F13/00 , G11C29/00
摘要： PURPOSE:To simplify the memory protecting mechanism by using in common the memory protecting systems of both the real and logic address systems. CONSTITUTION:Logic address LA or real address RA is stored in address register AR10. The RA or LA system is designated according to the logic state of output 104 of program state word 5. Based on this designation, switch circuit 12 selects the contents of expanded real segment NO.9 or AR10. Adder 17 performs the calculation which is necessary for the converting process from LA to RA, and the result of calculation is applied to register 18. The comparison 15 is given between the segment No. comprising AR10 and circuit 12 and the segment No. of one item of address converting buffer 13 designated by decoder 14. With the coincidence signal 102, control circuit 20 gives the control to the converting process from LA to RA. Ring protecting circuit 16 examines the ring protecting conditions based on buffer 13 and output 103 of word 5 and then delivers memory protecting exception signal 101.

2. 发明专利

JPS5576448A MULTIIGROUP REGISTER CONTROL SYSTEM 失效
公开(公告)号：JPS5576448A
公开(公告)日：1980-06-09
申请号：JP15075378
申请日：1978-12-05
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： NAKANO OSAMU , SAKAMA YASUO , ITOU KENICHI , YASUMI NAOAKI , KATOU MASAO , OOKAWA MASAYUKI
IPC分类号： G06F9/46 , G06F9/48
摘要： PURPOSE:To realize a high-efficiency data process by carrying out the shunt and recovery of the register contents through switching of the register groups when the optional program is switched. CONSTITUTION:Registers 0, I, II and III are arranged continuously in register memory 1; operation group pointer 2 designates the register group to be used; and intra-group pointer 3 designates the register to be used for the operation. Here in case the switching occurs for the optional program, the contents of pointer 2 is altered to perform switching of the register groups. In that case, a sufficient number of register groups are provided, and thus the control is given to the shunt and recovery of the register contents just through switching of the register groups. Thus the time can be shortened for the process of shunt and recovery, realizing a high-efficiency data process.

3. 发明专利

JPS5277544A ADDRESS TRANSITION CONTROL DEVICE 失效
公开(公告)号：JPS5277544A
公开(公告)日：1977-06-30
申请号：JP15431175
申请日：1975-12-23
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD
发明人： OOKAWA MASAYUKI , NAKAMURA IKUHIRO , YASUMI NAOAKI , KATOU MASAO
IPC分类号： G06F12/08 , G06F9/06 , G06F12/10 , G06F13/00
摘要： PURPOSE:To increase the using efficiency of a transition buffer device with a simple composition by such a way that the logical addresses are specified among the contents of the transition buffer and only a certain content become selectively invalid.

4. 发明专利

JPS5322330A ADDRESS CONVERSION SYSTEM 失效
公开(公告)号：JPS5322330A
公开(公告)日：1978-03-01
申请号：JP9607076
申请日：1976-08-13
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD , FUJITSU LTD
发明人： TSUKIOKA KENICHI , TAJIMA SEIJIROU , KATOU MASAO , OOKAWA MASAYUKI
IPC分类号： G06F12/10 , G06F9/34 , G06F12/02
摘要： PURPOSE:To use the segment table commonly when an address is converted to an actual address.

5. 发明专利

JPS5276841A INFORMATION PROCESSOR 失效
公开(公告)号：JPS5276841A
公开(公告)日：1977-06-28
申请号：JP15370175
申请日：1975-12-23
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： KINOUCHI YASUO , NAKAMURA TERUO , KATOU MASAO , OOKAWA MASAYUKI
IPC分类号： G06F12/08 , G06F13/00 , G06F15/16 , H02J1/00
摘要： PURPOSE:In the system having a plural number of CPU's it is arranged so that designation will become possible as to whether the coincidence processing of storing locations and stored information of memory betweens two given CPU's should be carried out or not, so that coincidence processing which is not wasteful can be carried out.

6. 发明专利

JPS58123150A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS58123150A
公开(公告)日：1983-07-22
申请号：JP560682
申请日：1982-01-18
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： IKEDA HITOSHI , OOKAWA MASAYUKI , FUKUOKA HIDEKI
IPC分类号： G06F11/16 , G01R31/3185 , G06F11/22 , G06F15/16 , G06F15/177
摘要： PURPOSE:To set or change automatically the state of a data processor, by reading the stored control information and then executing a process requested from the data processing side when the data processor delivers a maintenance instruction. CONSTITUTION:The address designated by the 2nd operand part is calculated by an operand address calculating circuit 11, and the OP code of an instruction set to a instruction register 10 is decoded by a decoder 20. When the OP code has the prescribed value, prescribed signal is transmitted to an interruption controlling circuit 21. Thus the circuit 21 turns on the prescribed interruption factor display bit of an interruption factor display register 22. An OR is secured for the contents of the register 22 through an interruption OR circuit 23 and then transmitted onto an interruption line 50. A scan-out control circuit 41 collects the scan-out data fed from each part of a data processor 100 and delivers them to a scan-out interface line 51.

7. 发明专利

JPS5169615A Kiokusochino shogaitsuchiseigyohoshiki 失效
标题翻译： KIOKUSOCHINO SHOGAITSUCHISEIGYOHOSHIKI
公开(公告)号：JPS5169615A
公开(公告)日：1976-06-16
申请号：JP14366674
申请日：1974-12-14
申请人： Fujitsu Ltd , Nippon Telegraph & Telephone
发明人： OOKAWA MASAYUKI , FURUTA SHIGEKI , NAKAMURA IKUHIRO , HAYASHI JUZO
IPC分类号： G06F12/16 , G06F11/30 , G11B5/09 , G11B20/18

8. 发明专利

JPS5654561A MEMORY INTERLEAVING CONTROL SYSTEM 失效
公开(公告)号：JPS5654561A
公开(公告)日：1981-05-14
申请号：JP13167879
申请日：1979-10-12
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TSUNODA HARUHIKO , OOKAWA MASAYUKI , HAYASHI YUUZOU , HAYAMIZU HARUO , FUKUOKA HIDEKI
IPC分类号： G06F12/06 , G06F13/00 , G11C8/00
摘要： PURPOSE:To make it possible to cope with extension as a user desires, by supplying a memory actuating circuit with the decision result of an interleaving decision part and interleaved bits and by determining a memory constituent unit to be accessed. CONSTITUTION:Address number comparison part 6 compares memory-constituting- unit corresponding bits in access address information, generated by access request device 3, with address number information. Then, interleaving decision part 7 decides the number of interleaved bits supplied by memories by interleaved bits and package/nonpackage discrimination flags in the access address information. The decision result of this decision part 7 and interleaved bits are supplied to memory actuating circuit 8 to determine the memory constituting unit to be accessed. Consequently, it is made possible to cope with the modification of the constitution of the memory unit freely and extension can also be coped with the desire of users.

9. 发明专利

JPS5794854A INTERRUPTION PROCESSING SYSTEM FOR COMPOSITE SYSTEM 失效
公开(公告)号：JPS5794854A
公开(公告)日：1982-06-12
申请号：JP17054280
申请日：1980-12-03
申请人： FUJITSU LTD
发明人： OOKAWA MASAYUKI , OKAMOTO TETSUO , OONISHI KATSUMI
IPC分类号： G06F9/38 , G06F9/46 , G06F9/48 , G06F11/07 , G06F11/14 , G06F15/16 , G06F15/177
摘要： PURPOSE:To assuredly perform the process of an interruption, etc., by fixing the instruction address return number and adding the instruction address return number to the contents of a present program counter when a pogram exceptional interruption conditions, etc. arises. CONSTITUTION:When a machine error is detected at a scholar unit 2, the unit 2 sends an instruction address return number alternation inhibiting command to a vector unit 3. Receiving this command, the unit 3 fixes the contents of an instruction counter 8 plus the contents of the program accessible registers.

10. 发明专利

JPS5619576A ADDRESS MATCHING DETECTION SYSTEM IN MULTIPLEESPACE PROCESSING DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS5619576A
公开(公告)日：1981-02-24
申请号：JP9451479
申请日：1979-07-25
申请人： FUJITSU LTD
发明人： OOKAWA MASAYUKI
IPC分类号： G06F12/10 , G06F13/00
摘要： PURPOSE:To simplify the constitution without increasing the hardware, by detecting the matching through the use of the space indicating information (iD) making effective the logic page-real page address corresponding table (TLB). CONSTITUTION:Only when the real address picked up from the TLB 4 according to the entry of the specified bits of the logic address from the logic address register 3 and the logic address of TLB4 are in coincidence with the comparison circuit 5, the selection circuit 7 performs effective processing. On the other hand, this circuit 7 is made effective when the iD designated at the space indication information register 2 at preset processing and the iD according to the logic address entry during processing at TLB4 are in agreement at the comparator 6. The address matching circuit is controlled with the flag signal set together with the iD by the register through the AND gate 9 open with the high level coincidence signal output by the comparator 6. Accordingly, the address matching is detected with existing comparators, the hardware can not be increased and the constitution can be simpler.

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