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1. 发明专利

JPS5276841A INFORMATION PROCESSOR 失效
公开(公告)号：JPS5276841A
公开(公告)日：1977-06-28
申请号：JP15370175
申请日：1975-12-23
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： KINOUCHI YASUO , NAKAMURA TERUO , KATOU MASAO , OOKAWA MASAYUKI
IPC分类号： G06F12/08 , G06F13/00 , G06F15/16 , H02J1/00
摘要： PURPOSE:In the system having a plural number of CPU's it is arranged so that designation will become possible as to whether the coincidence processing of storing locations and stored information of memory betweens two given CPU's should be carried out or not, so that coincidence processing which is not wasteful can be carried out.

2. 发明专利

JPS62130442A FILE SUBSYSTEM 失效
公开(公告)号：JPS62130442A
公开(公告)日：1987-06-12
申请号：JP27206485
申请日：1985-12-03
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SAKURAI NORIHIKO , YAMAGUCHI HIROSHI , KINOUCHI YASUO
IPC分类号： G06F12/08 , G06F12/16
摘要： PURPOSE:To reduce the load on a host device by accessing an external device when trouble occurs to a cache and accessing a target data block on the external storage device when a target process can be substituted. CONSTITUTION:A controller 2 is equipped with the cache 4 between a main memory device and the external memory device 3, a flag 241 which indicates whether access is already attained or not is provided for a cache trouble monitoring part 26 and the device 3, and a part which controls data transfer between the host controller 1, and the device 3 and cache 4 is further provided. Then, the monitor part 26 when detects the trouble of the cache 4 confirms the flag 241, when the device 43 is not accessed, the device 3 is accessed and when the device 3 is accessed, the device 1 is informed after its normal end as if the cache 1 were not accessed.

3. 发明专利

JPH06161800A DUAL ELECTRONIC COMPUTER 失效
公开(公告)号：JPH06161800A
公开(公告)日：1994-06-10
申请号：JP33660792
申请日：1992-11-24
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： YAMANE MICHIHIRO , HIRANO MASANORI , KINOUCHI YASUO
IPC分类号： G06F11/16 , G06F11/20
摘要： PURPOSE:To continue an arithmetic processing even if one central arithmetic processing unit in stand-by mode between 1st and 2nd central arithmetic processing units gets out of order in a dual electronic computer which has the 1st and 2nd central arithmetic processing units and 1st and 2nd memories for storing the results of arithmetic processing by the 1st and 2nd central processing units. CONSTITUTION:The 2nd central processing unit CPU-2 is provided with a cache memory CASH-2 and also an initializing means which initializes the 1st and 2nd central arithmetic processing units CPU-1 and CPU-2 as an in-use and a stand-by central arithmetic processing unit respectively, a means which saves a central arithmetic processing unit fault monitoring program in the cache memory CASH-2 from the 2nd memory MEM-2 during the initialization by the initializing means, and a memory isolating means which isolates the 2nd central arithmetic processing unit CPU-2 from the 2nd memory MEM-2 after the initialization by the initializing means.

4. 发明专利

JPH06149658A MULTIPLE MEMORY SPACE MANAGEMENT SYSTEM 失效
公开(公告)号：JPH06149658A
公开(公告)日：1994-05-31
申请号：JP30018792
申请日：1992-11-10
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SHIOZAWA TSUNEMICHI , KINOUCHI YASUO , HIRANO MASANORI
IPC分类号： G06F12/02 , G06F15/16 , G06F15/177
摘要： PURPOSE:To provide a multiple memory space management system capable of using respective processing units by switching plural memory spaces. CONSTITUTION:At the time of receiving a reading access from a processing unit 1, data equal to a value previously set in the unit 1 are transferred from a multispace mangement memory 3, and at the time of receiving a rewriting access from the unit 1, entry data equal to the value previously set up in the unit 1 are autonomously generated in the memory 3 and only the data in the memory 3 are rewritten.

5. 发明专利

JPH06149653A MEMORY SPACE MANAGEMENT SYSTEM FOR PLURAL VERSIONS 失效
公开(公告)号：JPH06149653A
公开(公告)日：1994-05-31
申请号：JP30018892
申请日：1992-11-10
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SHIOZAWA TSUNEMICHI , KINOUCHI YASUO , HIRANO MASANORI
IPC分类号： G06F12/00 , G06F12/06
摘要： PURPOSE:To provide a memory space management system for plural versions which can efficiently manage a memory space for plural versions. CONSTITUTION:At the time of receiving a reading access from a processing unit, a version equal or older (smaller) to/than a value set up in a version register 11 from a time/space managing memory 2 is transferred, and at the time of receiving a rewriting access from the unit 1, the data of a version equal to the value set up in the register 11 is autonomously generated in the memory 2 and only the data in the memory 2 are rewritten.

6. 发明专利

JPH08320849A DISTRIBUTED SYSTEM CONTROL METHOD 失效
公开(公告)号：JPH08320849A
公开(公告)日：1996-12-03
申请号：JP12791895
申请日：1995-05-26
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： HIRANO MASANORI , SHIOZAWA TSUNEMICHI , KINOUCHI YASUO , SUZUKI TAKASHI
IPC分类号： G06F15/16 , G06F12/00 , G06F15/177 , G06F17/30
摘要： PURPOSE: To level the load of database access processing between service control modules which have databases and directories by coping with variation in the load in the decentralized system consisting of the service control modules and plural communication control modules which perform transmission and reception control over transactions and the allocation of the transaction to the service control modules. CONSTITUTION: Communication control modules 1 and 2 measure response times from the transmission of requests to access databases 8 and 9 to the service control modules 3 and 4 to the reception of responses and display the allocation of retrieval processing to the directories 6 and 7 with allocation flags 10 and 11 on the basis of the response times. At this time, less retrieval processing are allocated to the service control module which is high in the load of database access processing and more directory retrieval processing are allocated to the service control module which is low in the load of the database data access processing.

7. 发明专利

JPH08278909A SYSTEM AND METHOD FOR HIGH RELIABILITY 失效
公开(公告)号：JPH08278909A
公开(公告)日：1996-10-22
申请号：JP8217595
申请日：1995-04-07
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： HIRANO MASANORI , SHIOZAWA TSUNEMICHI , KINOUCHI YASUO , SUZUKI TAKASHI
IPC分类号： G06F12/00
摘要： PURPOSE: To reduce the influence range of a transaction process in a fault processing and to make the reliability of the whole module high by providing a main memory fault informing means and a central processing means. CONSTITUTION: The module 2 performs a transaction process for itself at a 50% use rate. Thus, processors 3 and 4 are put in partial charge of the transaction process at a

8. 发明专利

JPH07248932A POLYPHASE MEMORY CONTROL METHOD 失效
公开(公告)号：JPH07248932A
公开(公告)日：1995-09-26
申请号：JP6554694
申请日：1994-03-09
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： HIRANO MASANORI , SHIOZAWA TSUNEMICHI , KINOUCHI YASUO
IPC分类号： G06F12/16 , G06F11/20 , H04L29/14
摘要： PURPOSE:To apply the method to a non-interruption information processing system and to perform a restarting processing and the changeover of a program, etc., in a short time. CONSTITUTION:A processor 1 provided with a space phase register 5 and a time phase register 4 and a polyphase memory 2 provided with plural memory spaces addressed by a space phase number and a time phase number are used and the processor 1 is operated by instructions on the addresses of the memory spaces addressed by the space phase number and the time phase number respectively set in the space phase register 5 and the time phase register 4 in the plural memory spaces. Also, in such a method, a time phase generation instruction, a memory space generation instruction, a memory space elimination instruction, an inter-memory-space transition instruction, an inter-memory-space operand access instruction and an inter-memory-space transfer instruction, etc., are executed and the data and address of information are written in the memory spaces by respectively performing data conversion and address conversion.

9. 发明专利

JPH02135522A MEMORY SUB-SYSTEM 失效
公开(公告)号：JPH02135522A
公开(公告)日：1990-05-24
申请号：JP28983588
申请日：1988-11-16
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： KINOUCHI YASUO , SAKURAI NORIHIKO , ARAI KYOICHI
IPC分类号： G06F3/06
摘要： PURPOSE:To speed up a large capacity transfer and to improve a small capacity random access performance by dynamically selecting an action to use the performance of a parallel transfer at the time of transfer at a larger capacity and an operation to use the performance of the independent operation unit when a small capacity high frequency access is executed while the operations are matched to the processing. CONSTITUTION:A controller 1 to control a memory is provided with a condition control table 11 in the internal part and a memory sub-system memory device 2 is composed of a data buffer 21, an alignment synchronizing detecting circuit 22, a coupling control circuit 23 of a data buffer and a memory medium 20. A mode to interlock plural arbitrary independent operable memory media 20 and execute reading and writing in parallel and a mode to access to one arbitrary independent operable memory medium 20 are set, and when the large capacity of transfer is executed, the constitution to use the merit of the parallel transfer is applied to the processing and dynamically selected and when a small capacity high frequency access is executed, the constitution to use the performance of the independent operation unit is applied to the processing and dynamically selected respectively. In such a manner, the high speed o the large capacity transfer and the improvement of the small capacity random access performance can be executed.

10. 发明专利

JPS6214247A CASH SUB-SYSTEM 失效
公开(公告)号：JPS6214247A
公开(公告)日：1987-01-22
申请号：JP15279785
申请日：1985-07-11
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： SAKURAI NORIHIKO , KINOUCHI YASUO , YAMAGUCHI HIROSHI
IPC分类号： G06F12/08 , G06F12/12
摘要： PURPOSE:To aim at high speed accessing at the time of the cash hitting by judging the data renewal in accordance with the frequency of the WRITE access to the block on the cash memory. CONSTITUTION:At a cash memory 330, plural blocks accessed previously on a direct access storage device (DASD) 35 are stored. A WRITE access frequency counting part 31, when the cash hitting of the WRITE access is detected by an entry table retrieving part 30, the WRITE access frequency is renewed, and stores it to a register 313. The maximum allowable value of the WRITE frequency is loaded to a register 312, and the WRITE access frequency value after renewal is set to a register 311 and the size is compared. When the access frequency after the renewal is not large, '1' is outputted to a signal line 41.

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