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1. 发明专利

JPH0623954B2 失效
公开(公告)号：JPH0623954B2
公开(公告)日：1994-03-30
申请号：JP6580985
申请日：1985-03-29
申请人： FUJITSU LTD
发明人： KITAMURA TOSHIAKI , SHIMIZU KAZUYUKI , OINAGA JUJI , OONISHI KATSUMI
IPC分类号： G06F9/30 , G06F1/04 , G06F9/00 , G06F9/38 , G06F15/00

2. 发明专利

JPH0578053B2 失效
公开(公告)号：JPH0578053B2
公开(公告)日：1993-10-28
申请号：JP16827185
申请日：1985-07-30
申请人： FUJITSU LTD
发明人： INOE AIICHIRO , OINAGA JUJI , OONISHI KATSUMI
IPC分类号： G06F9/38

3. 发明专利

JPH0464092B2 失效
公开(公告)号：JPH0464092B2
公开(公告)日：1992-10-13
申请号：JP7792085
申请日：1985-04-12
申请人： FUJITSU LTD
发明人： KOIKE AKISUMI , OINAGA JUJI , OONISHI KATSUMI
IPC分类号： G06F11/22 , G06F9/00 , G06F13/14

4. 发明专利

JPH0419575B2 失效
公开(公告)号：JPH0419575B2
公开(公告)日：1992-03-30
申请号：JP1215885
申请日：1985-01-25
申请人： FUJITSU LTD
发明人： INOE AIICHIRO , OINAGA JUJI , OONISHI KATSUMI
IPC分类号： G06F9/38 , G06F17/16

5. 发明专利

JPH0351016B2 失效
公开(公告)号：JPH0351016B2
公开(公告)日：1991-08-05
申请号：JP18106984
申请日：1984-08-30
申请人： FUJITSU LTD
发明人： OONISHI KATSUMI , OINAGA JUJI , NISHIDA HIDEHIKO
IPC分类号： G06F12/14 , G06F12/02 , G06F12/08 , G06F12/10 , G06F12/12
摘要： PURPOSE:To make a high speed access of a storage block data by dividing the main storage device area into a constant scale block, reading a small block data from a data storage method at the same time and outputting the logic sum. CONSTITUTION:A 4K byte is divided into two by a key storage device and constituted with key storage devices 10-0 and 10-1. A control lines 12, 13 controls a switch circuit 15. A 20 bit address signal is passed into an address line 14-0 if the control signal is 0, and into an address line 14-1 if it is 1 when the control line 13 specifies a 4K action mode. Thus, Data corresponding to 2K byte block of the specified block address from both key storage device 10-0, 10-1 where an address signal is entered is read, and a logic sum is summed by a logic sum circuit 16 and defined by a key register 3 and outputted to by a register 5.

6. 发明专利

JPH0219493B2 失效
公开(公告)号：JPH0219493B2
公开(公告)日：1990-05-02
申请号：JP26396184
申请日：1984-12-14
申请人： FUJITSU LTD
发明人： KITAMURA TOSHIAKI , OINAGA JUJI , OONISHI KATSUMI
IPC分类号： G06F9/22

7. 发明专利

JPH024011B2 失效
公开(公告)号：JPH024011B2
公开(公告)日：1990-01-25
申请号：JP3580484
申请日：1984-02-27
申请人： FUJITSU LTD
发明人： OOTSUYAMA KOHEI , OINAGA JUJI , OONISHI KATSUMI
IPC分类号： G06F9/48 , G06F9/38 , G06F9/46

8. 发明专利

JPS638492B2 失效
公开(公告)号：JPS638492B2
公开(公告)日：1988-02-23
申请号：JP21202183
申请日：1983-11-11
申请人： FUJITSU LTD
发明人： OONISHI KATSUMI , OINAGA JUJI
IPC分类号： G06F9/38

9. 发明专利

JPS60179845A INSTRUCTION REREADING CONTROL SYSTEM 失效
公开(公告)号：JPS60179845A
公开(公告)日：1985-09-13
申请号：JP3580484
申请日：1984-02-27
申请人： FUJITSU LTD
发明人： OOTSUYAMA KOUHEI , OINAGA YUUJI , OONISHI KATSUMI
IPC分类号： G06F9/48 , G06F9/38 , G06F9/46
摘要： PURPOSE:To reread an instruction from an optional flow and an optional stage by storing instruction length corresponding to an address for prereading the instruction and an instruction address calculated from an instruction pointer in registers consisting of shift registers respectively and calculating a leading address from both the corresponding registers. CONSTITUTION:An address for prereading an instruction in each eight bytes is stored in a prefetching instruction address register 13 and a value of ''8'' is stored in a PFK register. An adder 4 sets up an effective address in a register 5, so that a buffer 6 is retrieved and the instruction is fetched and read out by an instruction register 7. An instruction pointer 14 holds the relative pointer of an instruction to be executed. The output of the adder 15 is an instruction address flowing through a pipe line and sent to the instruction address registers 16-18 constituted of plural shift registers. The contents of the corresponding instruction length register 20 are sent to instruction length register 20 and a pair of instruction length is selected and added to obtain a rereading address.

10. 发明专利

JPS59177655A Operation by-pass control system 失效
标题翻译：操作旁路控制系统
公开(公告)号：JPS59177655A
公开(公告)日：1984-10-08
申请号：JP5311183
申请日：1983-03-29
申请人： Fujitsu Ltd
发明人： OONO MASAHITO , OONISHI KATSUMI
IPC分类号： G06F9/38
摘要： PURPOSE: To shorten the processing cycle by using an operation by-pass from an intermediate register when the operation result of a preceding instruction is used as the operand of a succeeding instruction in a central processing unit of the pipeline control system.
CONSTITUTION: Data of a storage control part 1 is inputted to an operating part 7 through an operand word register OWR2 and selectors 5 and 6. The operating part 7 uses data, which is inputted from a register group 9 through operand registers 3 and 4, and data from the OWR2 to execute the operation. An intermediate register 8' is provided besides an operation result register 8 in the operating part 7, and the operation result of the preceding instruction which is established before all of the operation result is established is stored in the register 8' and is inputted to selectors 5 and 6 by operation by-pass. Thus, the processing cycle is shortened.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：当前一条指令的运算结果用作管道控制系统的中央处理单元中后续指令的操作数时，通过使用中间寄存器的旁路操作来缩短处理周期。构成：存储控制部分1的数据通过操作数字寄存器OWR2和选择器5和6输入到操作部分7.操作部分7使用从寄存器组9通过操作数寄存器3和4输入的数据，和来自OWR2的数据执行操作。除了操作部分7中的操作结果寄存器8之外还提供了中间寄存器8'，并且在所有操作结果被建立之前建立的先前指令的操作结果被存储在寄存器8'中并被输入到选择器操作旁路5和6。因此，处理周期缩短。

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