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1. 发明专利

JPS5580872A MICROPROGRAM LOADING SYSTEM 失效
公开(公告)号：JPS5580872A
公开(公告)日：1980-06-18
申请号：JP15328578
申请日：1978-12-11
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD
发明人： WATANABE NOBUYUKI , TAJIMA SEIJIROU , HAYAMIZU HARUO , YASUMI NAOAKI , SUMIMOTO TSUTOMU
IPC分类号： G06F9/22 , G06F12/08
摘要： PURPOSE:To prevent the mistaken alteration for the region proper to the hardware of the control memory by inhibiting the writing of the contents of the main memory into the control memory in case the address to load the contents of the main memory into the control memory is outside the designation region. CONSTITUTION:An access is given to the address which is designated by effective address register 19 in accordance with the contents of program counter 17, and then the order is read out of main memory 1. The contents of register 16 designated by part of the order read out is used as the writing address to control memory 2 and then applied to comparator 11 via operand register 13 to be then compared with the set value of lower and upper limit region registers 9 and 10 of firm region 4 which is to be rewritten in accordance with the program of memory 2 to be applied to comparator 11. And in case the writing address is outside the firm region range, the writing is inhibited for the data given to memory 2 from memory 1 by the inhibition signal delivered from comparator 11. As a result, the alteration due to the mistaken program can be prevented for region 3 proer to the hardware of memory 2.

2. 发明专利

JPS5580140A INTERRCHANNEL COMMUNICATION SYSTEM 失效
公开(公告)号：JPS5580140A
公开(公告)日：1980-06-17
申请号：JP15355778
申请日：1978-12-11
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： NAKANO OSAMU , KANAME SHIGERU , YASUMI NAOAKI , FUJISAKI HIROO , NARITA YUUICHI
IPC分类号： G06F13/12 , G06F3/00 , G06F13/38 , G06F15/17
摘要： PURPOSE:To simplify multiple control over several channel programs by making it possible to execute a channel program while the execution of another program is in process, and also by eliminating the overhead of an interruption at the time of data transfer between data processor. CONSTITUTION:Between data processors 1 and 2 consisting of CPUs 22 and 21, channel units 3 and 4, and main memory unit 6, inter-channel coupler 5 is arranged and in accordance with input and output commands sent from units 3 and 4, data transfer is carried out. This coupler 5 is provided with circuit 8 on the side of channel coupler A of unit 1 and circuit 18 on the side of channel coupler B of unit 2 and when receiver circuit 9 of A-side circuit 8 receives an input-output command indicating the start of data transfer and a command corresponding to the command is not received from its party side, information is stored in temporary memory unit 13 connected to control circuit 12 to interrupt the execution of the command. When the corresponding command is received from the other processor in succession, the execution of the command is restarted by information stored in unit 13.

3. 发明专利

JPS55163698A MEMORY PROTECTING SYSTEM 失效
公开(公告)号：JPS55163698A
公开(公告)日：1980-12-19
申请号：JP7098579
申请日：1979-06-06
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD , FUJITSU LTD
发明人： YASUMI NAOAKI , SEIJI TAKAYUKI , SHIOKAWA SHIZUO , SUMIMOTO TSUTOMU , OOKAWA MASAYUKI
IPC分类号： G06F12/14 , G06F12/08 , G06F12/10 , G06F13/00 , G11C29/00
摘要： PURPOSE:To simplify the memory protecting mechanism by using in common the memory protecting systems of both the real and logic address systems. CONSTITUTION:Logic address LA or real address RA is stored in address register AR10. The RA or LA system is designated according to the logic state of output 104 of program state word 5. Based on this designation, switch circuit 12 selects the contents of expanded real segment NO.9 or AR10. Adder 17 performs the calculation which is necessary for the converting process from LA to RA, and the result of calculation is applied to register 18. The comparison 15 is given between the segment No. comprising AR10 and circuit 12 and the segment No. of one item of address converting buffer 13 designated by decoder 14. With the coincidence signal 102, control circuit 20 gives the control to the converting process from LA to RA. Ring protecting circuit 16 examines the ring protecting conditions based on buffer 13 and output 103 of word 5 and then delivers memory protecting exception signal 101.

4. 发明专利

JPS5576448A MULTIIGROUP REGISTER CONTROL SYSTEM 失效
公开(公告)号：JPS5576448A
公开(公告)日：1980-06-09
申请号：JP15075378
申请日：1978-12-05
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： NAKANO OSAMU , SAKAMA YASUO , ITOU KENICHI , YASUMI NAOAKI , KATOU MASAO , OOKAWA MASAYUKI
IPC分类号： G06F9/46 , G06F9/48
摘要： PURPOSE:To realize a high-efficiency data process by carrying out the shunt and recovery of the register contents through switching of the register groups when the optional program is switched. CONSTITUTION:Registers 0, I, II and III are arranged continuously in register memory 1; operation group pointer 2 designates the register group to be used; and intra-group pointer 3 designates the register to be used for the operation. Here in case the switching occurs for the optional program, the contents of pointer 2 is altered to perform switching of the register groups. In that case, a sufficient number of register groups are provided, and thus the control is given to the shunt and recovery of the register contents just through switching of the register groups. Thus the time can be shortened for the process of shunt and recovery, realizing a high-efficiency data process.

5. 发明专利

JPS55112622A CLOCK UNIT FOR INFORMATION PROCESSING SYSTEM 失效
公开(公告)号：JPS55112622A
公开(公告)日：1980-08-30
申请号：JP1834279
申请日：1979-02-21
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： MINAMI HIDEKAZU , HIRANO MASANORI , YASUMI NAOAKI , NARITA YUUICHI
IPC分类号： G04G7/00 , G04G5/00 , G06F1/00 , G06F1/14
摘要： PURPOSE:To reduce the interface signal lines between the first and second units, by setting the content of the upper rank digit of the clock circuit to the count circuit of a plurality of the second units, when the lower rank digit of the clock circuit of the first unit is a specific value. CONSTITUTION:In the information system consisting of the centralized monitor control unit CSC3 and a plurality of CPU4, the upper rank digit of the real time timer 2 of CSC3 is connected to the upper rank digit of the real time timer 1 of CPU 4 with the timer value supply line 15. To set the content of the timer 2 to the timer 1, it is made when the lower rank digit of the timer 2 is zero, and in this case, the zero detection circuit 7 delivers the signal 1 to the clock set instruction line 18 via the gate 13. When CPU4 is in stop state, the half state display FF9 is 1, the gate 14 is open, and the signal on the line 18 is delivered to the timer control circuit 10. When the circuit 10 delivers this information to the timer 1, the timer 1 sets the information on the line 15 to the upper rank digit and all 0 to the lower rank digit. Accordingly, since CSC supplies signals to CPU only at the upper rank digit of the real time timer, the interface between units can be reduced.

6. 发明专利

JPS5277544A ADDRESS TRANSITION CONTROL DEVICE 失效
公开(公告)号：JPS5277544A
公开(公告)日：1977-06-30
申请号：JP15431175
申请日：1975-12-23
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD
发明人： OOKAWA MASAYUKI , NAKAMURA IKUHIRO , YASUMI NAOAKI , KATOU MASAO
IPC分类号： G06F12/08 , G06F9/06 , G06F12/10 , G06F13/00
摘要： PURPOSE:To increase the using efficiency of a transition buffer device with a simple composition by such a way that the logical addresses are specified among the contents of the transition buffer and only a certain content become selectively invalid.

7. 发明专利

JPS55112621A CLOCK UNIT FOR INFORMATION PROCESSING SYSTEM 失效
公开(公告)号：JPS55112621A
公开(公告)日：1980-08-30
申请号：JP1834179
申请日：1979-02-21
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： MINAMI HIDEKAZU , HIRANO MASANORI , YASUMI NAOAKI , NARITA YUUICHI
IPC分类号： G06F1/14 , G04G99/00 , G06F1/00
摘要： PURPOSE:To enable the clock operation by the second unit even if the first unit is in failure, by incorporating the real time timer to each unit, in the information processing system consisting of the first unit and a plurality of the second units. CONSTITUTION:In the system consisting of the centralized monitor unit CSC3 and a plurality of CPU4, each unit incorporates the real timers 2, 1 respectively. The timer 2 counts the real time standard value of the timer 1 via the clock set instruction line 18 and the timer value supply line 15. If the CSC3 is normal, the signal of the clock effective display line 17 is 1, the selection circuit 11 selects the clock of the clock generation circuit 5, and if the CSC3 is in failure, the signal on the line 17 is 0 with the failure detection circuit 6, and the circuit 11 selects the clock of the clock generating circuit 12. The clock count clock from the circuit 11 is fed to the timer 1 via the timer control circuit 10.

8. 发明专利

JPS5556223A INTERRCOMPUTER COMMUNICATION SYSTEM 失效
公开(公告)号：JPS5556223A
公开(公告)日：1980-04-24
申请号：JP13015178
申请日：1978-10-23
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： SAKAGUCHI KATSUAKI , KOYANAZU IKUROU , YASUMI NAOAKI , YAMAGA MITSUHIRO , NARITA YUUICHI
IPC分类号： G06F13/12 , G06F3/00 , G06F13/38 , G06F15/16 , G06F15/17
摘要： PURPOSE:To make it possible to execute a different channel program while one channel program is being executed by a corresponding channel by shortening an in-use state of a channel as much as possible. CONSTITUTION:Data transfer starts by a coincidence between WRITE command (indication of CC) A from CH4-2 and READ command (no indication of CC) B from CH4-1. In accordance with contents of a flag indicated together with A, inter-computer coupler 5 reports only CHE as status information to 4-2 to release temporarily CHs 5 and 4-2 on an I/O interface from a coupling state. To 4-1, on the other hand, simultaneous report 21 of CHE and DUE in accordance with contents of a flag reported together with above-mentioned B cause an interruption of a processor (not shown in the figure) and also actuates 4-1 through coupler 5, so that when a coincidence with a device address corresponding to a channel program in an interruption state is obtained, the program will be restarted.

9. 发明专利

JPS5277550A INFORMATION PROCESSING UNIT 失效
公开(公告)号：JPS5277550A
公开(公告)日：1977-06-30
申请号：JP15431075
申请日：1975-12-23
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD
发明人： SHINOHARA MAKOTO , HIRAMATSU TAKUYA , YASUMI NAOAKI , KATOU MASAO
IPC分类号： G06F9/48 , G06F11/00 , G06F11/28
摘要： PURPOSE:To make variable the number of instructions, by making the debug operation every execution of the specified numbers and by developing interrupt signal when the number of instructions set arbitrarily in advance and the number of processing instructions counted are in agreement.

10. 发明专利

JPS54111733A MULTIPLEX PROCESSOR SYSTEM 失效
公开(公告)号：JPS54111733A
公开(公告)日：1979-09-01
申请号：JP1928678
申请日：1978-02-21
申请人： NIPPON ELECTRIC CO
发明人： YASUMI NAOAKI
IPC分类号： G06F11/20 , G06F9/46 , G06F15/16 , G06F15/177
摘要： PURPOSE:To increase the ratio of cost to performance, by executing the task represented for the priority having the highest priority by the processor designated with the processor designated information. CONSTITUTION:The system consists of the main memory 1, first and second processor 2, 3, and input and output channel unit 4 connected to I/O 5, and the process control block information used for the control of processor usage right is stored in the unit 1. Further, the porcessor 2 consists of the sequential control section 31, interruption control section 32, semaphore control section 33, control section 34 selecting the task to be executed, memory access circuit 35, operation circuit 36 and register 37, and control sections 31 and 32 requests the start of the control operation with the control section 34 while relating to the contrl sections 33, and if there is no task under execution with the processor 2, the task having the highest priority among the task group possible for execution is found and the task corresponding is out of linkage from the queue by rolling in it.

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