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1. 发明专利

JPH0568902B2 失效
公开(公告)号：JPH0568902B2
公开(公告)日：1993-09-29
申请号：JP19733385
申请日：1985-09-06
申请人： NIPPON ELECTRIC CO , HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： IBORI SHOICHI , YAMAGA MITSUHIRO , HOSHIKO TAKAYUKI , TSUNODA HARUHIKO
IPC分类号： H04L12/42

2. 发明专利

JPS5481731A CLOCK AND REFRESH CONTROL SYSTEM FOR DYNAMIC TYPE MEMORY 失效
公开(公告)号：JPS5481731A
公开(公告)日：1979-06-29
申请号：JP14973577
申请日：1977-12-13
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TSUNODA HARUHIKO , IIJIMA KIYOKATSU , KAWAKAMI TAKASHI , AOKI KATSUHIKO
IPC分类号： G06F9/52 , G06F15/16 , G06F15/167 , G06F15/177 , G11C11/406
摘要： PURPOSE:To enable to perform safety usage to a plurality of CPU's, by using the clock and refresh request signal of itself in place of the signal for the memory at CPU side, when the clock of the conditional signal representing the difference for the clock in use by each CPU is different. CONSTITUTION:The clock from CPUo and CPU1 delivered via the lines l1 and l2 at the memory side is received with the AND gates g100 and g101, and the refresh request signals RRO and RR1 are received with the AND gates g90 and g91. Then, the conditional signal representing the difference of the clock in use with each computer is fed from the computers CPUo and CPU1 to memory, and if the clock is different at the memory side, the clock and the refresh request signal from the refresh request circuit IRR and the internal clock oscillator ICO of itself are used in place of the clock and the refresh request signal from the computer side, allowing to perform safety use to a plurality of CPU's different in the clock.

3. 发明专利

JPS5798058A CONTROL SYSTEM FOR STORAGE DEVICE 失效
公开(公告)号：JPS5798058A
公开(公告)日：1982-06-18
申请号：JP17517480
申请日：1980-12-11
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： HAYAMIZU HARUO , AKAGI MASANOBU , YAMAGA MITSUHIRO , TSUNODA HARUHIKO
IPC分类号： G06F12/16 , G06F12/06
摘要： PURPOSE:To secure a prefix area and, simultaneously, prevent an access space from impossibleness of organization because of discontinuity of a floating space even if a storage device is in the workable condition by automatically setting a floating address corresponding to the condition of a storage unit, then securing a prefix area. CONSTITUTION:A computer system consists of a CPU11 and a storage devices 12 and 13, and the devices 12 and 13 are provided with plural number of storage devices U1-Un and floating address registers R1-Rn to set a floating address. These devices and the CPU11 are connected by a signal line 14. On the other hand, the devices 12 and 13 are provided with an operation check circuit 21 that checks for normal working through investigating the steady state of the power supply for the storage device itself, the state of trouble on each storage unit U1 and Un, etc., and its state signal is input to the floating address set circuit 20 mounted on the CPU11 through the signal line 14. Then, the floating address from the CPU11 are set to registers R1-Rn by the floating address set circuit 22.

4. 发明专利

JPS5654561A MEMORY INTERLEAVING CONTROL SYSTEM 失效
公开(公告)号：JPS5654561A
公开(公告)日：1981-05-14
申请号：JP13167879
申请日：1979-10-12
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TSUNODA HARUHIKO , OOKAWA MASAYUKI , HAYASHI YUUZOU , HAYAMIZU HARUO , FUKUOKA HIDEKI
IPC分类号： G06F12/06 , G06F13/00 , G11C8/00
摘要： PURPOSE:To make it possible to cope with extension as a user desires, by supplying a memory actuating circuit with the decision result of an interleaving decision part and interleaved bits and by determining a memory constituent unit to be accessed. CONSTITUTION:Address number comparison part 6 compares memory-constituting- unit corresponding bits in access address information, generated by access request device 3, with address number information. Then, interleaving decision part 7 decides the number of interleaved bits supplied by memories by interleaved bits and package/nonpackage discrimination flags in the access address information. The decision result of this decision part 7 and interleaved bits are supplied to memory actuating circuit 8 to determine the memory constituting unit to be accessed. Consequently, it is made possible to cope with the modification of the constitution of the memory unit freely and extension can also be coped with the desire of users.

5. 发明专利

JPS523347A REFRESH CONTROL SYSTEM IN MEMORY 失效
公开(公告)号：JPS523347A
公开(公告)日：1977-01-11
申请号：JP7904575
申请日：1975-06-24
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： ICHINOGE TOSHIO , KOBAYASHI MASAMITSU , IIJIMA KIYOKATSU , TSUNODA HARUHIKO
IPC分类号： G06F12/16 , G06F12/00 , G11C11/406
摘要： PURPOSE:A refresh control system for dynamic type memory in common employed in plural memories.

6. 发明专利

JPS6258745A MULTIPLE ADDRESS COMMUNICATION SYSTEM 失效
公开(公告)号：JPS6258745A
公开(公告)日：1987-03-14
申请号：JP19733385
申请日：1985-09-06
申请人： NEC CORP , HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： IBORI SHOICHI , YAMAGA MITSUHIRO , HOSHIKO TAKAYUKI , TSUNODA HARUHIKO
IPC分类号： H04L12/42
摘要： PURPOSE:To attain a resending even in the multiple address communication of loop-shaped network by starting up a timer means for a looped supervision in a multiple address frame transmission time at a transmission side and starting up a resending means by a time-out. CONSTITUTION:A station A starts up the transmission of a multiple address command frame and at the same time, it starts up a looped supervisory timer T1 (timer time is Ta) and a timer T2 (timer time is Tb) that queues a data transmission. The station A that has detected the time-out of the looped supervisory time T1 performs the resending by number of times regulated within the timer time Tb. Meanwhile, at a receiving station, a station that has received the first multiple address command frame starts up a multiple address receiving data frame queuing supervisory timer T4 (timer time is T4) and receives only a multiple address data frame different from the multiple address command frame. When the multiple address data frame is not received within the timer time T4, the supervisory timer T4 is reset, thereby terminating a multiple address receiving operation.

7. 发明专利

JPS57127998A DETECTION SYSTEM FOR DISCONNECTION OF FAILED UNIT 失效
公开(公告)号：JPS57127998A
公开(公告)日：1982-08-09
申请号：JP1257681
申请日：1981-01-30
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： IIJIMA KIYOKATSU , TSUNODA HARUHIKO , KOBAYASHI MASAMITSU , KANEDA SHIGEO
IPC分类号： G06F12/16 , G06F11/20 , G11C29/04
摘要： PURPOSE:To detect failure of individual memory unit with less hardware constitution, by collating the result of failure detection at a common unit failure detection section in each storage device with that a storage device failure detection section at an access side device. CONSTITUTION:In a data processing system linking storage devices 2A-2N sectioning storage area into a plurality of units and an access side device to them with buses 7A-7N, unit failure detection sections 4A, 5A common to each unit are provided on a bus, e.g., 6A where readout data from each unit is commonly given in each storage device. In the access side device 1 where the readout data is transferred via a bus, storage device failure detection sections 14, 15 are provided, the result of failure detection by the unit failure detection section is transferred to the access side device and the result is collated with that at the storage device failure detection section, allowing to discriminate the failure in each unit.

8. 发明专利

JPS59178545A Error detecting system 失效
标题翻译：错误检测系统
公开(公告)号：JPS59178545A
公开(公告)日：1984-10-09
申请号：JP5419983
申请日：1983-03-30
申请人： Fujitsu Ltd
发明人： EGAWA HIROYUKI , TSUNODA HARUHIKO
IPC分类号： G06F11/00
CPC分类号： G06F11/0751
摘要： PURPOSE:To enable detection of error simultaneously with access when error occurs there irrespective of a part or whole of data by unifying error detection output line. CONSTITUTION:When a register stack is in a word access mode, an inversion byte line 12 is in on state. Under this condition, word address is given to a decoder 5 to access word s. By this, a high level signal is sent out to the word address s line. Accordingly, a signal is outputted from an AND gate 11 and passes through an OR gate 10 to access a register through a line 13. If the word s is word 1, the register is accessed, and the output is given to a corresponding error detecting circuit 2, and presence of error is checked for each byte.
摘要翻译：目的：通过统一错误检测输出线，使错误发生时能够同时访问错误，无论是部分或全部数据。构成：当寄存器堆栈处于字访问模式时，反转字节行12处于开状态。在这种情况下，字地址被给予解码器5访问字s。由此，将高电平信号发送到字地址线。因此，从与门11输出信号并通过或门10通过线路13访问寄存器。如果字s为字1，则访问寄存器，并将输出给予相应的错误检测电路2，并检查每个字节是否存在错误。

9. 发明专利

JPS59176845A Address stack control method of memory 失效
标题翻译：存储器的地址堆栈控制方法
公开(公告)号：JPS59176845A
公开(公告)日：1984-10-06
申请号：JP5184283
申请日：1983-03-28
申请人： Fujitsu Ltd
发明人： HAGIWARA TETSUYA , TSUNODA HARUHIKO , SHIMADA TOSHIO
IPC分类号： G06F9/42 , G06F13/00
摘要： PURPOSE: To detect a fault of a program and to prevent previously the runaway of the program by comparing the indicated value with the set value of a memory for address stack the address stack controlling.
CONSTITUTION: When a subroutine operation is carried out, a reset address A is held at the first address of an address stack memory 1 and also stored in a register 4. With the next subroutine call, and address B is stacked to the second address. A reset address X is stacked to the (n-1)th address of the memory 1, and then a subroutine call address is read out. Under such conditions, a stack pointer 2 indicates the zero address of the memory 1. In this case, a comparator 5 detects that the address A is coincident with the initial value address held at the register 4 and then stops the progress of a program.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：为了检测程序的故障，并通过将指示的值与地址堆栈的存储器的设置值进行比较来预防程序的失控，地址堆栈的控制。构成：当执行子程序操作时，复位地址A保存在地址堆栈存储器1的第一个地址处，并存储在寄存器4中。通过下一个子程序调用，并将地址B堆叠到第二个地址。复位地址X被堆叠到存储器1的第（n-1）个地址，然后读出子程序调用地址。在这种情况下，堆栈指针2表示存储器1的零地址。在这种情况下，比较器5检测到地址A与保持在寄存器4的初始值地址一致，然后停止程序的进行。

10. 发明专利

JPS6045867A INFORMATION PROCESSOR 失效
公开(公告)号：JPS6045867A
公开(公告)日：1985-03-12
申请号：JP15280183
申请日：1983-08-22
申请人： FUJITSU LTD
发明人： EITAI YOSHIHIRO , TSUNODA HARUHIKO
IPC分类号： G06F13/14 , G06F13/36
摘要： PURPOSE:To always check the state of connection between a controller and a device to be controlled by providing an executing circuit for specific instruction between these two devices and putting the connection information of the device to be controlled on a data bus. CONSTITUTION:A specific instruction is sent to devices 3-6 to be controlled from a controller 1 via an instruction bus. Then the devices 3-6 reads their connection information through each instruction decoding part to identify a specific instruction and select the connection information transfer system of their own through multiplexers 7-10 to send the output of selection to a data bus 2. In this case, if the address data is transmitted to select one of devices 3-6, the device to be controlled is specified by the corresponding address. Then the connection information is sent to a specific bit position on the bus 2, and the corresponding data is read by the controller 1. Thus the state of connection is decided for devices 3-6 respectively.

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